Adding note about the patching of the UDI and UDS

Signed-off-by: Joachim Strömbergson <[email protected]>

hw/application_fpga/core/tk1/README.md

@@ -121,6 +121,15 @@ Each SB_LUT4 MUX is able to store 16 bits of data, in total 512
 bits. But since the UDI is 64 bits, we only use the two LSBs in each
 MUX.
 
+During build of the FPGA design, the UDI is set to a known bit
+pattern, which means that the SB_LUT4 instantiations are initialized
+to a fixed bit pattern.
+
+The tool 'patch_uds_udi.py' is used to replace the fixed bit pattern
+with a unique bit pattern before generating the per device unique FPGA
+bitstream. This allows us to generate these device unique FPGA
+bitstreams without haveing to do a full FPGA build.
+
 
 ### RAM memory protecion
 

hw/application_fpga/core/uds/README.md

@@ -42,6 +42,15 @@ The eight UDS words are stored using 32 named SB_LUT4 FPGA multiplexer
 (MUX) instances, identified in the source code as "uds\_rom\_idx". One
 instance for each bit in the core read_data output bus.
 
+During build of the FPGA design, the UDS is set to a known bit
+pattern, which means that the SB_LUT4 instantiations are initialized
+to a fixed bit pattern.
+
+The tool 'patch_uds_udi.py' is used to replace the fixed bit pattern
+with a unique bit pattern before generating the per device unique FPGA
+bitstream. This allows us to generate these device unique FPGA
+bitstreams without haveing to do a full FPGA build.
+
 Each SB_LUT4 MUX is able to store 16 bits of data, in total 512
 bits. But since the UDS is 256 bits, we only use the eight LSBs in
 each MUX.