FPGA: Increase UART baud rate to 500k

tillitis · Oct 9, 2024 · 3b983d2 · 3b983d2
1 parent 2f42989
commit 3b983d2
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
@@ -83,10 +83,10 @@ module uart(
   // The default bit rate is based on target clock frequency
   // divided by the bit rate times in order to hit the
   // center of the bits. I.e.
-  // Clock: 18 MHz, 62500 bps
-  // Divisor = 18E6 / 62500 = 288
+  // Clock: 18 MHz, 500 Kbps
+  // Divisor = 18E6 / 500E3 = 36
   // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
-  localparam DEFAULT_BIT_RATE  = 16'd288;
+  localparam DEFAULT_BIT_RATE  = 16'd36;
   localparam DEFAULT_DATA_BITS = 4'h8;
   localparam DEFAULT_STOP_BITS = 2'h1;