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Merge pull request #5152 from bardliao/merge/sound-upstream-20240822
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Merge/sound upstream 20240822
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bardliao authored Aug 23, 2024
2 parents f2d0899 + 2aea00e commit 82543d8
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1 change: 1 addition & 0 deletions .mailmap
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Expand Up @@ -166,6 +166,7 @@ Daniel Borkmann <[email protected]> <[email protected]>
Daniel Borkmann <[email protected]> <[email protected]>
David Brownell <[email protected]>
David Collins <[email protected]> <[email protected]>
David Heidelberg <[email protected]> <[email protected]>
David Rheinsberg <[email protected]> <[email protected]>
David Rheinsberg <[email protected]> <[email protected]>
David Rheinsberg <[email protected]> <[email protected]>
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6 changes: 3 additions & 3 deletions Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu
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Expand Up @@ -32,9 +32,9 @@ Description: (RW) The front button on the Turris Omnia router can be
interrupt.

This file switches between these two modes:
- "mcu" makes the button press event be handled by the MCU to
change the LEDs panel intensity.
- "cpu" makes the button press event be handled by the CPU.
- ``mcu`` makes the button press event be handled by the MCU to
change the LEDs panel intensity.
- ``cpu`` makes the button press event be handled by the CPU.

Format: %s.

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3 changes: 2 additions & 1 deletion Documentation/ABI/testing/sysfs-devices-system-cpu
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Expand Up @@ -562,7 +562,8 @@ Description: Control Symmetric Multi Threading (SMT)
================ =========================================

If control status is "forceoff" or "notsupported" writes
are rejected.
are rejected. Note that enabling SMT on PowerPC skips
offline cores.

What: /sys/devices/system/cpu/cpuX/power/energy_perf_bias
Date: March 2019
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2 changes: 1 addition & 1 deletion Documentation/admin-guide/cifs/usage.rst
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Expand Up @@ -742,7 +742,7 @@ SecurityFlags Flags which control security negotiation and
may use NTLMSSP 0x00080
must use NTLMSSP 0x80080
seal (packet encryption) 0x00040
must seal (not implemented yet) 0x40040
must seal 0x40040

cifsFYI If set to non-zero value, additional debug information
will be logged to the system error log. This field
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15 changes: 8 additions & 7 deletions Documentation/admin-guide/device-mapper/dm-crypt.rst
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Expand Up @@ -162,13 +162,14 @@ iv_large_sectors


Module parameters::
max_read_size
max_write_size
Maximum size of read or write requests. When a request larger than this size
is received, dm-crypt will split the request. The splitting improves
concurrency (the split requests could be encrypted in parallel by multiple
cores), but it also causes overhead. The user should tune these parameters to
fit the actual workload.

max_read_size
max_write_size
Maximum size of read or write requests. When a request larger than this size
is received, dm-crypt will split the request. The splitting improves
concurrency (the split requests could be encrypted in parallel by multiple
cores), but it also causes overhead. The user should tune these parameters to
fit the actual workload.


Example scripts
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4 changes: 1 addition & 3 deletions Documentation/admin-guide/kernel-parameters.txt
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Expand Up @@ -4798,11 +4798,9 @@

profile= [KNL] Enable kernel profiling via /proc/profile
Format: [<profiletype>,]<number>
Param: <profiletype>: "schedule", "sleep", or "kvm"
Param: <profiletype>: "schedule" or "kvm"
[defaults to kernel profiling]
Param: "schedule" - profile schedule points.
Param: "sleep" - profile D-state sleeping (millisecs).
Requires CONFIG_SCHEDSTATS
Param: "kvm" - profile VM exits.
Param: <number> - step/bucket size as a power of 2 for
statistical time based profiling.
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18 changes: 18 additions & 0 deletions Documentation/arch/arm64/silicon-errata.rst
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Expand Up @@ -122,10 +122,18 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A76 | #1490853 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #1491015 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
Expand All @@ -138,8 +146,14 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1 | #1502854 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
Expand All @@ -160,6 +174,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
Expand All @@ -170,6 +186,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #1619801 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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36 changes: 22 additions & 14 deletions Documentation/arch/riscv/hwprobe.rst
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Expand Up @@ -239,25 +239,33 @@ The following keys are defined:
ratified in commit 98918c844281 ("Merge pull request #1217 from
riscv/zawrs") of riscv-isa-manual.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
mistakenly classified as a bitmask rather than a value.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
accesses is unknown.
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing
the performance of misaligned scalar native word accesses on the selected set
of processors.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
emulated via software, either in or below the kernel. These accesses are
always extremely slow.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of
misaligned scalar accesses is unknown.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower
than equivalent byte accesses. Misaligned accesses may be supported
directly in hardware, or trapped and emulated by software.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
accesses are emulated via software, either in or below the kernel. These
accesses are always extremely slow.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster
than equivalent byte accesses.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
word sized accesses are slower than the equivalent quantity of byte
accesses. Misaligned accesses may be supported directly in hardware, or
trapped and emulated by software.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
not supported at all and will generate a misaligned address fault.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
word sized accesses are faster than the equivalent quantity of byte
accesses.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
accesses are not supported at all and will generate a misaligned address
fault.

* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicboz block in bytes.
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3 changes: 3 additions & 0 deletions Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
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Expand Up @@ -35,6 +35,9 @@ properties:
ports-implemented:
const: 1

power-domains:
maxItems: 1

sata-port@0:
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port

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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm display clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8994

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6125

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6115

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6125

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks and power domains on
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm camera clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm display clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 Video Clock & Reset Controller

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm video clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM8450

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6375 Display MDSS

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel

maintainers:
- Konrad Dybcio <konradybcio@gmail.com>
- Konrad Dybcio <konradybcio@kernel.org>

description: |+
This panel seems to only be found in the Asus Z00T
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7 changes: 5 additions & 2 deletions Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
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Expand Up @@ -17,9 +17,12 @@ properties:
oneOf:
# Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
- const: samsung,atna33xc20
# Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
- items:
- const: samsung,atna45af01
- enum:
# Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
- samsung,atna45af01
# Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
- samsung,atna45dc02
- const: samsung,atna33xc20

enable-gpios: true
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/panel/sony,td4353-jdi.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/eeprom/at25.yaml
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Expand Up @@ -28,6 +28,7 @@ properties:
- anvo,anv32e61w
- atmel,at25256B
- fujitsu,mb85rs1mt
- fujitsu,mb85rs256
- fujitsu,mb85rs64
- microchip,at25160bn
- microchip,25lc040
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280

maintainers:
- Bjorn Andersson <[email protected]>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP

maintainers:
- Bjorn Andersson <[email protected]>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450

maintainers:
- Bjorn Andersson <[email protected]>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies legacy IOMMU implementations

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm "B" family devices which are not compatible with arm-smmu have
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4 changes: 4 additions & 0 deletions Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
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Expand Up @@ -38,6 +38,10 @@ properties:

managed: true

phys:
description: A reference to the SerDes lane(s)
maxItems: 1

required:
- reg

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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MDM9607 TLMM block

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
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