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29 changes: 29 additions & 0 deletions
29
include/ttmlir/Dialect/TTNN/Transforms/Workarounds/Decomposition/ArgMaxOpRewritePattern.h
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| // SPDX-FileCopyrightText: (c) 2025 Tenstorrent AI ULC | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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| #ifndef TTMLIR_DIALECT_TTNN_TRANSFORMS_WORKAROUNDS_DECOMPOSITION_ARGMAXOPREWRITEPATTERN_H | ||
| #define TTMLIR_DIALECT_TTNN_TRANSFORMS_WORKAROUNDS_DECOMPOSITION_ARGMAXOPREWRITEPATTERN_H | ||
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| #include "ttmlir/Dialect/TTNN/IR/TTNNOps.h" | ||
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| #include "mlir/IR/PatternMatch.h" | ||
| #include "mlir/Support/LogicalResult.h" | ||
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| namespace mlir::tt::ttnn::workarounds::decomposition { | ||
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| // tt-metal supports ArgMax op for 4D tensors only. | ||
| // https://github.com/tenstorrent/tt-metal/issues/18241 | ||
| // This workaround unsqueeze the input tensor to 4D tennsor (if required) and | ||
| // reshape it back to original shape after performing the ArgMax op. | ||
| class ArgMaxOpRewritePattern : public OpRewritePattern<ttnn::ArgMaxOp> { | ||
| public: | ||
| using OpRewritePattern<ttnn::ArgMaxOp>::OpRewritePattern; | ||
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| LogicalResult matchAndRewrite(ttnn::ArgMaxOp srcOp, | ||
| PatternRewriter &rewriter) const override; | ||
| }; | ||
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| } // namespace mlir::tt::ttnn::workarounds::decomposition | ||
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| #endif // TTMLIR_DIALECT_TTNN_TRANSFORMS_WORKAROUNDS_DECOMPOSITION_ARGMAXOPREWRITEPATTERN_H |
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96 changes: 96 additions & 0 deletions
96
lib/Dialect/TTNN/Transforms/Workarounds/Decomposition/ArgMaxOpRewritePattern.cpp
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| // SPDX-FileCopyrightText: (c) 2025 Tenstorrent AI ULC | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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| #include "ttmlir/Dialect/TTNN/Transforms/Workarounds/Decomposition/ArgMaxOpRewritePattern.h" | ||
| #include "ttmlir/Conversion/TTIRToTTNN/Utils.h" | ||
| #include "ttmlir/Dialect/TT/IR/TTOpsTypes.h" | ||
| #include "ttmlir/Dialect/TTNN/IR/TTNNOps.h" | ||
| #include "ttmlir/Dialect/TTNN/IR/TTNNOpsAttrs.h" | ||
| #include "ttmlir/Dialect/TTNN/Utils/TransformUtils.h" | ||
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| #include "mlir/IR/BuiltinAttributes.h" | ||
| #include "mlir/IR/Value.h" | ||
| #include "mlir/Support/LLVM.h" | ||
| #include "llvm/ADT/ArrayRef.h" | ||
| #include "llvm/ADT/SmallVector.h" | ||
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| namespace mlir::tt::ttnn::workarounds::decomposition { | ||
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| LogicalResult | ||
| ArgMaxOpRewritePattern::matchAndRewrite(ttnn::ArgMaxOp srcOp, | ||
| PatternRewriter &rewriter) const { | ||
| mlir::RankedTensorType inputType = | ||
| mlir::cast<RankedTensorType>(srcOp.getInput().getType()); | ||
| llvm::SmallVector<int64_t> inputTypeShape(inputType.getShape()); | ||
| if (inputTypeShape.size() >= 4) { | ||
| return failure(); | ||
| } | ||
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| int64_t inputRank = inputType.getRank(); | ||
| llvm::SmallVector<int64_t, 4> reshapeOutputShape(4 - inputRank, 1); | ||
| reshapeOutputShape.append(inputTypeShape.begin(), inputTypeShape.end()); | ||
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| llvm::ArrayRef<int64_t> reshapedShapeAttr(reshapeOutputShape); | ||
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| ReshapeOp preReshapeOp = ttir_to_ttnn::utils::generateReshape( | ||
| srcOp.getInput(), reshapedShapeAttr, rewriter); | ||
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| RankedTensorType outputType = srcOp.getResult().getType(); | ||
| llvm::SmallVector<int64_t> outputTypeShape(outputType.getShape()); | ||
| llvm::SmallVector<int64_t, 4> argMaxOutputShape(4 - inputRank, 1); | ||
| argMaxOutputShape.append(outputTypeShape.begin(), outputTypeShape.end()); | ||
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| ttnn::TTNNLayoutAttr newOutputLayoutAttr = | ||
| mlir::cast<ttnn::TTNNLayoutAttr>(outputType.getEncoding()) | ||
| .withTensorShape(rewriter.getContext(), argMaxOutputShape); | ||
| RankedTensorType newOutputType = RankedTensorType::get( | ||
| argMaxOutputShape, outputType.getElementType(), newOutputLayoutAttr); | ||
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| DataTypeAttr dTypeAttr = DataTypeAttr::get(rewriter.getContext(), | ||
| newOutputLayoutAttr.getDataType()); | ||
| ttnn::LayoutAttr tensorLayoutAttr = | ||
| ttnn::LayoutAttr::get(getContext(), newOutputLayoutAttr.getLayout()); | ||
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| ttnn::ShapeAttr shapeAttr = | ||
| ttnn::ShapeAttr::get(rewriter.getContext(), newOutputType.getShape()); | ||
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| ttnn::BufferTypeAttr bufferTypeAttr = ttnn::BufferTypeAttr::get( | ||
| getContext(), newOutputLayoutAttr.getBufferType()); | ||
| ttnn::ShardSpecAttr shardSpecAttr = ttnn::ShardSpecAttr::get( | ||
| getContext(), | ||
| ttnn::ShapeAttr::get(getContext(), newOutputLayoutAttr.getShardShape())); | ||
| ttnn::MemoryConfigAttr memoryConfigAttr = | ||
| ttnn::MemoryConfigAttr::get(getContext(), bufferTypeAttr, shardSpecAttr, | ||
| newOutputLayoutAttr.getMemLayout()); | ||
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| EmptyOp emptyOp = rewriter.create<ttnn::EmptyOp>( | ||
| srcOp->getLoc(), newOutputType, shapeAttr, dTypeAttr, tensorLayoutAttr, | ||
| ttnn::utils::getOrInsertDevice(rewriter, srcOp), memoryConfigAttr); | ||
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| mlir::IntegerAttr dimAttr; | ||
| auto dimArg = srcOp.getDim(); | ||
| if (dimArg) { | ||
| // Update the dimension according to reshaped input. | ||
| int32_t dim = *dimArg + (reshapeOutputShape.size() - inputTypeShape.size()); | ||
| dimAttr = | ||
| mlir::IntegerAttr::get(mlir::IntegerType::get(getContext(), 32), dim); | ||
| } | ||
| ArgMaxOp argMaxOp = rewriter.create<mlir::tt::ttnn::ArgMaxOp>( | ||
| srcOp->getLoc(), newOutputType, preReshapeOp->getResult(0), | ||
| dimArg ? dimAttr : nullptr, false, nullptr, emptyOp); | ||
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| llvm::ArrayRef<int64_t> outputShapeAttr(outputType.getShape()); | ||
| mlir::TypedValue<mlir::RankedTensorType> argMaxOutput = | ||
| mlir::cast<mlir::TypedValue<mlir::RankedTensorType>>( | ||
| argMaxOp->getResults().front()); | ||
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| ReshapeOp postReshapeOp = ttir_to_ttnn::utils::generateReshape( | ||
| argMaxOutput, outputShapeAttr, rewriter); | ||
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| rewriter.replaceOp(srcOp, postReshapeOp); | ||
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| return success(); | ||
| } | ||
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| } // namespace mlir::tt::ttnn::workarounds::decomposition |
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43 changes: 43 additions & 0 deletions
43
test/ttmlir/Dialect/TTNN/Transforms/Workarounds/argmax_workaround.mlir
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| // RUN: ttmlir-opt --ttnn-workaround --canonicalize %s | FileCheck %s | ||
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| #device = #tt.device<workerGrid = #tt.grid<8x8, (d0, d1) -> (0, d0, d1)>, l1Map = (d0, d1)[s0, s1] -> (0, d0 floordiv s0, d1 floordiv s1, (d0 mod s0) * s1 + d1 mod s1), dramMap = (d0, d1)[s0, s1] -> (0, 0, ((((d0 floordiv s0) * 8 + d1 floordiv s1) * (s1 * s0) + (d0 mod s0) * s1 + d1 mod s1) floordiv 8192) mod 12, (((d0 floordiv s0) * 8 + d1 floordiv s1) * (s1 * s0) + (d0 mod s0) * s1 + d1 mod s1) floordiv 98304 + (((d0 floordiv s0) * 8 + d1 floordiv s1) * (s1 * s0) + (d0 mod s0) * s1 + d1 mod s1) mod 8192), meshShape = , chipIds = [0]> | ||
| #dram = #ttnn.buffer_type<dram> | ||
| #system_desc = #tt.system_desc<[{role = host, target_triple = "x86_64-pc-linux-gnu"}], [{arch = <wormhole_b0>, grid = 8x8, l1_size = 1499136, num_dram_channels = 12, dram_channel_size = 1073741824, noc_l1_address_align_bytes = 16, pcie_address_align_bytes = 32, noc_dram_address_align_bytes = 32, l1_unreserved_base = 1024, erisc_l1_unreserved_base = 1024, dram_unreserved_base = 1024, dram_unreserved_end = 1073741824, physical_cores = {worker = [ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 1x0, 1x1, 1x2, 1x3, 1x4, 1x5, 1x6, 1x7, 2x0, 2x1, 2x2, 2x3, 2x4, 2x5, 2x6, 2x7, 3x0, 3x1, 3x2, 3x3, 3x4, 3x5, 3x6, 3x7, 4x0, 4x1, 4x2, 4x3, 4x4, 4x5, 4x6, 4x7, 5x0, 5x1, 5x2, 5x3, 5x4, 5x5, 5x6, 5x7, 6x0, 6x1, 6x2, 6x3, 6x4, 6x5, 6x6, 6x7, 7x0, 7x1, 7x2, 7x3, 7x4, 7x5, 7x6, 7x7] dram = [ 8x0, 9x0, 10x0, 8x1, 9x1, 10x1, 8x2, 9x2, 10x2, 8x3, 9x3, 10x3]}, supported_data_types = [<f32>, <f16>, <bf16>, <bfp_f8>, <bfp_bf8>, <bfp_f4>, <bfp_bf4>, <bfp_f2>, <bfp_bf2>, <u32>, <u16>, <u8>], supported_tile_sizes = [ 4x16, 16x16, 32x16, 4x32, 16x32, 32x32], num_cbs = 32}], [0], [3 : i32], [ 0x0x0x0]> | ||
| #ttnn_layout = #ttnn.ttnn_layout<(d0, d1) -> (d0, d1), <1x1>, memref<2x2x!tt.tile<32x32, f32>, #dram>, <interleaved>> | ||
| #ttnn_layout1 = #ttnn.ttnn_layout<(d0, d1) -> (d0, d1), <1x1>, memref<2x1x!tt.tile<32x32, u32>, #dram>, <interleaved>> | ||
| module attributes {tt.device = #device, tt.system_desc = #system_desc} { | ||
| func.func public @argmax_2d(%arg0: tensor<64x64xf32, #ttnn_layout>) -> tensor<64x1xui32, #ttnn_layout1> { | ||
| %0 = "ttnn.get_device"() <{mesh_shape = #ttnn<mesh_shape 1x1>}> : () -> !tt.device<#device> | ||
| // CHECK: %[[PRE_RESHAPE:[0-9]+]] = "ttnn.reshape"(%arg0) | ||
| // CHECK-SAME: {shape = [1 : i32, 1 : i32, 64 : i32, 64 : i32]} | ||
| // CHECK-SAME: tensor<64x64xf32, | ||
| // CHECK-SAME: -> tensor<1x1x64x64xf32 | ||
| // CHECK: %[[ARG0:[0-9]+]] = "ttnn.to_layout"(%[[PRE_RESHAPE]], | ||
| // CHECK-SAME: dtype = #tt.supportedDataTypes<bf16> | ||
| // CHECK-SAME: layout = #ttnn.layout<row_major> | ||
| // CHECK-SAME: tensor<1x1x64x64xf32, | ||
| // CHECK-SAME: -> tensor<1x1x64x64xbf16, | ||
| // CHECK: %[[ARG1:[0-9]]] = "ttnn.to_layout" | ||
| // CHECK-SAME: dtype = #tt.supportedDataTypes<u32> | ||
| // CHECK-SAME: layout = #ttnn.layout<row_major> | ||
| // CHECK-SAME: tensor<1x1x64x1xui32 | ||
| // CHECK-SAME: -> tensor<1x1x64x1xui32 | ||
| %1 = "ttnn.empty"(%0) <{dtype = #tt.supportedDataTypes<u32>, layout = #ttnn.layout<tile>, memory_config = #ttnn.memory_config<#dram, <<2x1>>, <interleaved>>, shape = #ttnn.shape<64x1>}> : (!tt.device<#device>) -> tensor<64x1xui32, #ttnn_layout1> | ||
| // CHECK: [[ARG_MAX:[0-9]+]] = "ttnn.argmax"(%[[ARG0]], %[[ARG1]]) | ||
| // CHECK-SAME: {dim = 3 : i32, use_multicore = false} | ||
| // CHECK-SAME: tensor<1x1x64x64xbf16 | ||
| // CHECK-SAME: tensor<1x1x64x1xui32 | ||
| // CHECK-SAME: -> tensor<1x1x64x1xui32 | ||
| %2 = "ttnn.argmax"(%arg0, %1) <{dim = 1 : i32, use_multicore = false}> : (tensor<64x64xf32, #ttnn_layout>, tensor<64x1xui32, #ttnn_layout1>) -> tensor<64x1xui32, #ttnn_layout1> | ||
| // CHECK: %[[TO_LAYOUT:[0-9]+]] = "ttnn.to_layout"(%[[ARG_MAX]], | ||
| // CHECK-SAME: dtype = #tt.supportedDataTypes<u32> | ||
| // CHECK-SAME: layout = #ttnn.layout<tile> | ||
| // CHECK-SAME: (tensor<1x1x64x1xui32 | ||
| // CHECK-SAME: -> tensor<1x1x64x1xui32 | ||
| // CHECK: = "ttnn.reshape"(%[[TO_LAYOUT]]) | ||
| // CHECK-SAME: {shape = [64 : i32, 1 : i32]} | ||
| // CHECK-SAME: tensor<1x1x64x1xui32 | ||
| // CHECK-SAME: -> tensor<64x1xui32 | ||
| return %2 : tensor<64x1xui32, #ttnn_layout1> | ||
| } | ||
| } |
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