Merge pull request #273 from slaclab/pre-release

Release Candidate v4.5.0

.flake8

@@ -1,42 +1,65 @@
 [flake8]
-exclude = __init__.py
 #############################################################
 # Note: Comamnd to remove white space at the end of lines
 # $ find . -type f -name "*.py" -print0 | xargs -0 sed -i 's/\s*$//g'
 #############################################################
-# E116 unexpected indentation (comment)
-# E128 continuation line under-indented for visual indent
-# E131 continuation line unaligned for hanging indent
-# E201 whitespace after '('
-# E202 whitespace before ')'
-# E203 whitespace before ':'
-# E211 whitespace before '('
-# E221 multiple spaces before operator
-# E222 multiple spaces after operator
-# E225 missing whitespace around operator
-# E226 missing whitespace around arithmetic operator
-# E227 missing whitespace around bitwise or shift operator
-# E228 missing whitespace around modulo operator
-# E231 missing whitespace after ','
-# E241 multiple spaces after ','
-# E251 unexpected spaces around keyword / parameter equals
-# E261 at least two spaces before inline comment
-# E262 inline comment should start with '# '
-# E265 block comment should start with '# '
-# E266 too many leading '#' for block comment
-# E272 multiple spaces before keyword
-# E302 expected 2 blank lines, found 1
-# E303 too many blank lines
-# E305 expected 2 blank lines after class or function definition
-# E306 expected 1 blank line before a nested definition, found 0
-# E501 line too long
-# W605 invalid escape sequence
-# E713 test for membership should be 'not in'
-# E722 do not use bare 'except'
-#############################################################
-ignore = E116,E128,E131,\
-         E201,E202,E203,E211,E221,E222,E225,E226,E227,E228,E231,E241,E251,E261,E262,E265,E266,E272,\
-         E302,E303,E305,E306,\
-         E501,\
-         W605,\
-         E722,E713
+exclude = __init__.py
+extend-ignore =
+   # E116: unexpected indentation (comment)
+   E116,
+   # E128: continuation line under-indented for visual indent
+   E128,
+   # E131: continuation line unaligned for hanging indent
+   E131,
+   # E201: whitespace after '('
+   E201,
+   # E202: whitespace before ')'
+   E202,
+   # E203: whitespace before ':'
+   E203,
+   # E211: whitespace before '('
+   E211,
+   # E221: multiple spaces before operator
+   E221,
+   # E222: multiple spaces after operator
+   E222,
+   # E225: missing whitespace around operator
+   E225,
+   # E226: missing whitespace around arithmetic operator
+   E226,
+   # E227: missing whitespace around bitwise or shift operator
+   E227,
+   # E228: missing whitespace around modulo operator
+   E228,
+   # E231: missing whitespace after ','
+   E231,
+   # E241: multiple spaces after ','
+   E241,
+   # E251: unexpected spaces around keyword / parameter equals
+   E251,
+   # E261: at least two spaces before inline comment
+   E261,
+   # E262: inline comment should start with '# '
+   E262,
+   # E265: block comment should start with '# '
+   E265,
+   # E266: too many leading '#' for block comment
+   E266,
+   # E272: multiple spaces before keyword
+   E272,
+   # E302: expected 2 blank lines, found 1
+   E302,
+   # E303: too many blank lines
+   E303,
+   # E305: expected 2 blank lines after class or function definition
+   E305,
+   # E306: expected 1 blank line before a nested definition, found 0
+   E306,
+   # E501: line too long
+   E501,
+   # W605: invalid escape sequence
+   W605,
+   # E713: test for membership should be 'not in'
+   E713,
+   # E722: do not use bare 'except'
+   E722

cadence/genus/env_var.tcl

@@ -0,0 +1,26 @@
+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+########################################################
+## Set Common Environmental variables
+########################################################
+
+# Project Variables
+set DESIGN           $::env(PROJECT)
+set PROJECT          $::env(PROJECT)
+set PRJ_VERSION      $::env(PRJ_VERSION)
+set PROJ_DIR         $::env(PROJ_DIR)
+set TOP_DIR          $::env(TOP_DIR)
+set IMAGES_DIR       $::env(IMAGES_DIR)
+set IMAGENAME        $::env(IMAGENAME)
+set OUT_DIR          $::env(OUT_DIR)
+set SYN_DIR          $::env(SYN_DIR)
+set SYN_OUT_DIR      $::env(SYN_OUT_DIR)
+set RUCKUS_DIR       $::env(RUCKUS_DIR)

cadence/genus/proc.tcl

@@ -0,0 +1,224 @@
+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_DIR)/shared/proc.tcl
+
+## Returns the FPGA family string
+proc getFpgaFamily { } {
+   # Legacy Vivado function: not-supported
+   return "not-supported"
+}
+
+## Returns the FPGA family string
+proc getFpgaArch { } {
+   # Legacy Vivado function: not-supported
+   return "not-supported"
+}
+
+## Returns true is Versal
+proc isVersal { } {
+   # Legacy Vivado function: not-supported
+   return false;
+}
+
+###############################################################
+#### Loading Source Code Functions ############################
+###############################################################
+
+## Open ruckus.tcl file
+proc loadRuckusTcl { filePath {flags ""} } {
+   puts "loadRuckusTcl: ${filePath} ${flags}"
+   # Make a local copy of global variable
+   set LOC_PATH $::DIR_PATH
+   # Make a local copy of global variable
+   set ::DIR_PATH ${filePath}
+   # Open the TCL file
+   if { [file exists ${filePath}/ruckus.tcl] == 1 } {
+      source ${filePath}/ruckus.tcl
+   } else {
+      puts "\n\n\n\n\n********************************************************"
+      puts "loadRuckusTcl: ${filePath}/ruckus.tcl doesn't exist"
+      puts "********************************************************\n\n\n\n\n"
+      exit -1
+   }
+   # Revert the global variable back to original value
+   set ::DIR_PATH ${LOC_PATH}
+}
+
+## Reset source file lists
+proc ResetSrcFileLists {} {
+   set ::SRC_VHDL     ""
+   set ::SRC_VERILOG  ""
+   set ::SRC_SVERILOG ""
+}
+
+## Update source file lists
+proc UpdateSrcFileLists {filepath} {
+   set fileExt [file extension ${filepath}]
+   if { ${fileExt} eq {.vhd} ||
+        ${fileExt} eq {.vhdl} } {
+      set ::SRC_VHDL "$::SRC_VHDL ${filepath}"
+   } elseif {
+        ${fileExt} eq {.v} ||
+        ${fileExt} eq {.vh} } {
+      set ::SRC_VERILOG "$::SRC_VERILOG ${filepath}"
+   } else {
+      set ::SRC_SVERILOG "$::SRC_SVERILOG ${filepath}"
+   }
+}
+
+## Analyze source file lists
+proc AnalyzeSrcFileLists args {
+   # Parse the list of args
+   array set params $args
+
+   # Initialize local variables
+   set vhdlTop ""
+   set verilogTop ""
+   set systemVerilogTop ""
+   set vhdlLib ""
+   set verilogLib ""
+   set systemVerilogLib ""
+
+   if {[info exists params(-vhdlTop)]} {
+     set vhdlTop "$params(-vhdlTop)"
+   }
+
+   if {[info exists params(-verilogTop)]} {
+      set verilogTop "$params(-verilogTop)"
+   }
+
+   if {[info exists params(-systemVerilogTop)]} {
+      set systemVerilogTop "$params(-systemVerilogTop)"
+   }
+
+   if {[info exists params(-vhdlLib)]} {
+      set vhdlLib "$params(-vhdlLib)"
+   }
+
+   if {[info exists params(-verilogLib)]} {
+      set verilogLib "$params(-verilogLib)"
+   }
+
+   if {[info exists params(-systemVerilogLib)]} {
+      set systemVerilogLib "$params(-systemVerilogLib)"
+   }
+
+   # Load VHDL code to memory
+   if { $::SRC_VHDL  != "" } {
+      read_hdl -language vhdl -library ${vhdlLib} "$::SRC_VHDL"
+   }
+
+   # Load Verilog code to memory
+   if { $::SRC_VERILOG  != "" } {
+      read_hdl "$::SRC_VERILOG"
+   }
+
+   # Load System Verilog code to memory
+   if { $::SRC_SVERILOG  != "" } {
+      read_hdl -sv "$::SRC_SVERILOG"
+   }
+
+   # Reset source file lists
+   ResetSrcFileLists
+}
+
+## Function to load RTL files
+proc loadSource args {
+
+   # Strip out the -sim_only flag
+   if {[string match {*-sim_only*} $args]} {
+      set args [string map {"-sim_only" ""} $args]
+      # Not support simulation source code in design compiler yet
+      return
+   }
+
+   # Parse the list of args
+   array set params $args
+
+   if {![info exists params(-path)]} {
+      set has_path 0
+   } else {
+      set has_path 1
+   }
+
+   if {![info exists params(-dir)]} {
+      set has_dir 0
+   } else {
+      set has_dir 1
+   }
+
+   if {![info exists params(-lib)]} {
+      set lib "work"
+   } else {
+      set lib $params(-lib)
+   }
+
+   # Check for error state
+   if {${has_path} && ${has_dir}} {
+      puts "\n\n\n\n\n********************************************************"
+      puts "loadSource: Cannot specify both -path and -dir"
+      puts "********************************************************\n\n\n\n\n"
+      exit -1
+   # Load a single file
+   } elseif {$has_path} {
+      # Check if file doesn't exist
+      if { [file exists $params(-path)] != 1 } {
+         puts "\n\n\n\n\n********************************************************"
+         puts "loadSource: $params(-path) doesn't exist"
+         puts "********************************************************\n\n\n\n\n"
+         exit -1
+      } else {
+         # Check the file extension
+         set fileExt [file extension $params(-path)]
+         if { ${fileExt} eq {.vhd} ||
+              ${fileExt} eq {.vhdl}||
+              ${fileExt} eq {.v}   ||
+              ${fileExt} eq {.vh}  ||
+              ${fileExt} eq {.sv} } {
+            # Update source file list
+            UpdateSrcFileLists $params(-path)
+         } else {
+            puts "\n\n\n\n\n********************************************************"
+            puts "loadSource: $params(-path) does not have a \[.vhd,.vhdl,.v,.vh,.sv\] file extension"
+            puts "********************************************************\n\n\n\n\n"
+            exit -1
+         }
+      }
+   # Load all files from a directory
+   } elseif {$has_dir} {
+      # Check if directory doesn't exist
+      if { [file exists $params(-dir)] != 1 } {
+         puts "\n\n\n\n\n********************************************************"
+         puts "loadSource: $params(-dir) doesn't exist"
+         puts "********************************************************\n\n\n\n\n"
+         exit -1
+      } else {
+         # Get a list of all RTL files
+         set list ""
+         set list_rc [catch {
+            set list [glob -directory $params(-dir) *.vhd *.vhdl *.v *.vh *.sv]
+         } _RESULT]
+         # Load all the RTL files
+         if { ${list} != "" } {
+            foreach pntr ${list} {
+               # Update source file list
+               UpdateSrcFileLists ${pntr}
+            }
+         } else {
+            puts "\n\n\n\n\n********************************************************"
+            puts "loadSource: $params(-dir) directory does not have any \[.vhd,.vhdl,.v,.vh,.sv,.dat,.coe,.mem,.edif,.dcp\] files"
+            puts "********************************************************\n\n\n\n\n"
+            exit -1
+         }
+      }
+   }
+}
+

cadence/genus/sim.sh

@@ -0,0 +1,32 @@
+#!/usr/bin/env bash
+# ----------------------------------------------------------------------------
+# This file is part of the 'SLAC Firmware Standard Library'. It is subject to
+# the license terms in the LICENSE.txt file found in the top-level directory
+# of this distribution and at:
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+# No part of the 'SLAC Firmware Standard Library', including this file, may be
+# copied, modified, propagated, or distributed except according to the terms
+# contained in the LICENSE.txt file.
+# ----------------------------------------------------------------------------
+
+# --- Compile StdCells
+vlogan $SIM_CARGS_VERILOG $STD_CELL_LIB
+
+# Check for custom user source code setup
+if [ -f "$PROJ_DIR/sim/sim.sh" ]; then
+   source $PROJ_DIR/sim/sim.sh
+
+# Else use the default simulation code structure
+else
+
+   # --- Compile post-synthesis sources
+   vlogan $SIM_CARGS_VERILOG $SYN_OUT_DIR/${PROJECT}_g.v
+
+   # --- Compile the system verilog simulation testbed
+   vlogan -sverilog $SIM_CARGS_VERILOG $SIM_SV_TESTBED
+
+   # Run the testbench
+   vcs tb_${PROJECT} $SIM_VCS_FLAGS -fgp -timescale=$SIM_TIMESCALE
+   ./simv -gui=dve -fgp=num_threads:$MAX_CORES +vcs+initreg+0
+
+fi