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Merge pull request #288 from slaclab/pre-release
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Release Candidate v4.7.0
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ruck314 authored Mar 6, 2023
2 parents 4a79614 + 05a68dc commit 5396980
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42 changes: 42 additions & 0 deletions cadence/genus/messages.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
##############################################################################
## This file is part of 'SLAC Firmware Standard Library'.
## It is subject to the license terms in the LICENSE.txt file found in the
## top-level directory of this distribution and at:
## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
## No part of 'SLAC Firmware Standard Library', including this file,
## may be copied, modified, propagated, or distributed except according to
## the terms contained in the LICENSE.txt file.
##############################################################################

# Warning : Declaration is ignored for synthesis. [VHDL-667]
# Declaration 'TPD_G' of physical type 'TIME'
suppress_messages { VHDL-667 }

# Warning : Ignoring 'after' clause in signal assignment. [VHDL-616]
suppress_messages { VHDL-616 }

# Warning : Assertion statements are ignored for synthesis. [VHDL-644]
suppress_messages { VHDL-644 }

# Warning : Concurrent assertion statements are ignored for synthesis. [VHDL-645]
suppress_messages { VHDL-645 }

# Warning : Initial values are ignored for synthesis. [VHDL-639]
suppress_messages { VHDL-639 }

# Warning : Report statements are ignored for synthesis. [VHDL-643]
suppress_messages { VHDL-643 }

# Warning : Ignoring unsynthesizable delay specifier (#<n>) mentioned in verilog file.
# These delay numbers are for simulation purpose only. [VLOGPT-35]
# in file 'surf/i2cSlave.sv' on line 401, column 20.
suppress_messages { VLOGPT-35 }

# Warning : Real value rounded to nearest integral value. [CDFG-371]
# : Real value XXX.000000 rounded to nearest integer value XXX
suppress_messages { CDFG-371 }

# Check for user messages.tcl script
if { [file exists $::env(PROJ_DIR)/syn/messages.tcl] == 1 } {
source $::env(PROJ_DIR)/syn/messages.tcl
}
104 changes: 47 additions & 57 deletions cadence/genus/proc.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -52,82 +52,73 @@ proc loadRuckusTcl { filePath {flags ""} } {
set ::DIR_PATH ${LOC_PATH}
}

## Reset source file lists
proc ResetSrcFileLists {} {
set ::SRC_VHDL ""
set ::SRC_VERILOG ""
set ::SRC_SVERILOG ""
}

## Update source file lists
proc UpdateSrcFileLists {filepath} {
set fileExt [file extension ${filepath}]
proc UpdateSrcFileLists {filepath lib} {
set path ${filepath}
set fileExt [file extension ${path}]
set fbasename [file tail ${path}]
if { ${fileExt} eq {.vhd} ||
${fileExt} eq {.vhdl} } {
set ::SRC_VHDL "$::SRC_VHDL ${filepath}"
set SRC_TYPE "SRC_VHDL"
} elseif {
${fileExt} eq {.v} ||
${fileExt} eq {.vh} } {
set ::SRC_VERILOG "$::SRC_VERILOG ${filepath}"
set SRC_TYPE "SRC_VERILOG"
} else {
set ::SRC_SVERILOG "$::SRC_SVERILOG ${filepath}"
set SRC_TYPE "SRC_SVERILOG"
}
exec mkdir -p $::env(OUT_DIR)/${SRC_TYPE}
exec mkdir -p $::env(OUT_DIR)/${SRC_TYPE}/${lib}
exec ln -s ${path} $::env(OUT_DIR)/${SRC_TYPE}/${lib}/${fbasename}
}

## Analyze source file lists
proc AnalyzeSrcFileLists args {
# Parse the list of args
array set params $args

# Initialize local variables
set vhdlTop ""
set verilogTop ""
set systemVerilogTop ""
set vhdlLib ""
set verilogLib ""
set systemVerilogLib ""
proc AnalyzeSrcFileLists { } {

if {[info exists params(-vhdlTop)]} {
set vhdlTop "$params(-vhdlTop)"
}

if {[info exists params(-verilogTop)]} {
set verilogTop "$params(-verilogTop)"
}

if {[info exists params(-systemVerilogTop)]} {
set systemVerilogTop "$params(-systemVerilogTop)"
if {[file exist $::env(OUT_DIR)/SRC_VHDL]} {
set vhdlDir ""
foreach dir [glob -type d $::env(OUT_DIR)/SRC_VHDL/*] {
set vhdlLib [file tail ${dir}]
set vhdlDir "${vhdlDir} -x ${vhdlLib}:${dir}"
}
exec cd $::env(OUT_DIR)/SRC_VHDL; vhdeps dump "${vhdlDir}" -o $::env(OUT_DIR)/SRC_VHDL/order
set fp [open $::env(OUT_DIR)/SRC_VHDL/order r]
set file_data [read $fp]
close $fp
set vhdlOrderList [split $file_data "\n"]
foreach line ${vhdlOrderList} {
if { ${line} != ""} {
set vhdlLib [lindex [split ${line}] 1]
set filePath [lindex [split ${line}] 3]
read_hdl -language vhdl -library ${vhdlLib} ${filePath}
}
}
}

if {[info exists params(-vhdlLib)]} {
set vhdlLib "$params(-vhdlLib)"
}
if {[file exist $::env(OUT_DIR)/SRC_VERILOG]} {

if {[info exists params(-verilogLib)]} {
set verilogLib "$params(-verilogLib)"
}
set srcList ""
foreach dir [glob -type d $::env(OUT_DIR)/SRC_VERILOG/*] {
foreach filePath [glob -type f ${dir}/*] {
set srcList "${srcList} ${filePath}"
}
}
read_hdl ${srcList}

if {[info exists params(-systemVerilogLib)]} {
set systemVerilogLib "$params(-systemVerilogLib)"
}

# Load VHDL code to memory
if { $::SRC_VHDL != "" } {
read_hdl -language vhdl -library ${vhdlLib} "$::SRC_VHDL"
}
if {[file exist $::env(OUT_DIR)/SRC_SVERILOG]} {

# Load Verilog code to memory
if { $::SRC_VERILOG != "" } {
read_hdl "$::SRC_VERILOG"
}
set srcList ""
foreach dir [glob -type d $::env(OUT_DIR)/SRC_SVERILOG/*] {
foreach filePath [glob -type f ${dir}/*] {
set srcList "${srcList} ${filePath}"
}
}
read_hdl -sv ${srcList}

# Load System Verilog code to memory
if { $::SRC_SVERILOG != "" } {
read_hdl -sv "$::SRC_SVERILOG"
}

# Reset source file lists
ResetSrcFileLists
}

## Function to load RTL files
Expand Down Expand Up @@ -184,7 +175,7 @@ proc loadSource args {
${fileExt} eq {.vh} ||
${fileExt} eq {.sv} } {
# Update source file list
UpdateSrcFileLists $params(-path)
UpdateSrcFileLists $params(-path) ${lib}
} else {
puts "\n\n\n\n\n********************************************************"
puts "loadSource: $params(-path) does not have a \[.vhd,.vhdl,.v,.vh,.sv\] file extension"
Expand All @@ -210,7 +201,7 @@ proc loadSource args {
if { ${list} != "" } {
foreach pntr ${list} {
# Update source file list
UpdateSrcFileLists ${pntr}
UpdateSrcFileLists ${pntr} ${lib}
}
} else {
puts "\n\n\n\n\n********************************************************"
Expand All @@ -221,4 +212,3 @@ proc loadSource args {
}
}
}

7 changes: 6 additions & 1 deletion cadence/genus/syn.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -12,9 +12,13 @@
source $::env(RUCKUS_GENUS_DIR)/proc.tcl
source $::env(RUCKUS_GENUS_DIR)/env_var.tcl

# Check if we are suppressing messages
if { [expr {[info exists ::env(SUPRESS_MSG)] && [string is true -strict $::env(SUPRESS_MSG)]}] } {
source ${RUCKUS_DIR}/cadence/genus/messages.tcl
}

# Init the global variable
set ::DIR_PATH ""
ResetSrcFileLists

# Setup local variables
set design ${DESIGN}
Expand Down Expand Up @@ -73,6 +77,7 @@ if { [file exists ${PROJ_DIR}/syn/export.tcl] == 1 } {
# Copy the .sdf, sdc, .v, and reports to project image directory
exec cp -f ${SYN_OUT_DIR}/${design}_g.sdf ${IMAGES_DIR}/${IMAGENAME}.sdf
exec cp -f ${SYN_OUT_DIR}/${design}_g.sdc ${IMAGES_DIR}/${IMAGENAME}.sdc
exec cp -r ${SYN_OUT_DIR}/${design}_g.v ${IMAGES_DIR}/${IMAGENAME}.v
exec rm -rf ${IMAGES_DIR}/reports
exec cp -rf ${SYN_OUT_DIR}/reports ${IMAGES_DIR}/.

Expand Down
3 changes: 3 additions & 0 deletions fabulous/proc.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,9 @@ proc CopyFabricHdlFiles { } {
exec cp -f ${filePath} $::env(HDL_DIR)/.
}

if { [file exists $::env(PROJ_DIR)/post_fabric.tcl] == 1 } {
source $::env(PROJ_DIR)/post_fabric.tcl
}
puts "\n\neFPGA HDL files copied to $::env(HDL_DIR)\n\n"
}

Expand Down
3 changes: 3 additions & 0 deletions synopsys/design_compiler/env_var.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -28,3 +28,6 @@ set OUT_DIR $::env(OUT_DIR)
set SYN_DIR $::env(SYN_DIR)
set SYN_OUT_DIR $::env(SYN_OUT_DIR)
set RUCKUS_DIR $::env(RUCKUS_DIR)

set design ${DESIGN}
set pdk_dir ${DIG_TECH}
4 changes: 0 additions & 4 deletions synopsys/design_compiler/syn.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,6 @@ source $::env(RUCKUS_DC_DIR)/env_var.tcl
set ::DIR_PATH ""
ResetSrcFileLists

# Setup local variables
set design ${DESIGN}
set pdk_dir ${DIG_TECH}

# Set the number of maximum cores
set_host_option -max_cores ${MAX_CORES}

Expand Down
2 changes: 1 addition & 1 deletion system_cadence_genus.mk
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ test:
#### Build Location ###########################################
###############################################################
.PHONY : dir
dir:
dir: clean
@test -d $(TOP_DIR)/build/ || { \
echo ""; \
echo "Build directory missing!"; \
Expand Down
19 changes: 9 additions & 10 deletions system_fabulous.mk
Original file line number Diff line number Diff line change
Expand Up @@ -118,20 +118,11 @@ dir:
echo ""; false; }
@rm -rf $(OUT_DIR)

###############################################################
#### Build nextpnr ############################################
###############################################################
.PHONY : nextpnr
nextpnr: dir
$(call ACTION_HEADER,"Fabulous: Build nextpnr")
@cd $(FAB_ROOT)/nextpnr; cmake . -DARCH=generic; make -j$(nproc)
@cd $(FAB_ROOT)/nextpnr; cmake . -DARCH=fabulous; make -j$(nproc)

###############################################################
#### Create Project ###########################################
###############################################################
.PHONY : proj
proj: nextpnr
proj: dir
$(call ACTION_HEADER,"Fabulous: Create Project")
@cd $(TOP_DIR)/build; python3 $(PYFAB) -c $(PROJECT)
@cp -f $(PROJ_DIR)/fabric.csv $(OUT_DIR)/.
Expand All @@ -152,6 +143,14 @@ fabric: proj
$(call ACTION_HEADER,"Fabulous: Generate the eFPGA fabric")
@cd $(TOP_DIR)/build; export DUMP_HDL=1; python3 $(PYFAB) -s $(RUCKUS_DC_DIR)/build.tcl $(PROJECT)

###############################################################
#### Interactive Mode #######################################
###############################################################
.PHONY : interactive
interactive : proj
$(call ACTION_HEADER,"Fabulous Interactive")
@cd $(TOP_DIR)/build; python3 $(PYFAB) $(PROJECT)

###############################################################
#### Clean ####################################################
###############################################################
Expand Down

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