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Merge pull request #174 from slaclab/gtrxaligncheck-dev
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Use SURF GtRxAlignCheck rather than local version
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@ruck314
ruck314 authored Jan 10, 2025
2 parents 7ee3709 + 3f1e5c2 commit 3ef7796
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Showing 10 changed files with 40 additions and 68 deletions.
4 changes: 1 addition & 3 deletions LCLS-II/evr/rtl/EvrV2CorePulseGen.vhd
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Expand Up @@ -342,9 +342,7 @@ begin -- rtl
Out_Trigger: for i in 0 to TriggerOutputs-1 generate
U_Trig : entity lcls_timing_core.EvrV2Trigger
generic map ( TPD_G => TPD_G,
CHANNELS_C => ReadoutChannels,
--DEBUG_C => (i<1) )
DEBUG_C => false )
CHANNELS_C => ReadoutChannels)
port map ( clk => evrClk,
rst => evrRst,
config => triggerConfigS(i),
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3 changes: 1 addition & 2 deletions LCLS-II/evr/rtl/EvrV2Module.vhd
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Expand Up @@ -177,8 +177,7 @@ begin -- rtl
U_Trig : entity lcls_timing_core.EvrV2Trigger
generic map ( TPD_G => TPD_G,
CHANNELS_C => NCHANNELS_G,
TRIG_DEPTH_C => TRIG_DEPTH_G,
DEBUG_C => false )
TRIG_DEPTH_C => TRIG_DEPTH_G)
port map ( clk => evrClk,
rst => evrRst,
config => triggerConfig(i),
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19 changes: 2 additions & 17 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_extref.xci
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Expand Up @@ -821,28 +821,13 @@
"C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexuplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku15p" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "15" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_extref" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
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17 changes: 1 addition & 16 deletions LCLS-II/gthUltraScale+/coregen/TimingGth_fixedlat.xci
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Expand Up @@ -821,26 +821,11 @@
"C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexuplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku15p" } ],
"PACKAGE": [ { "value": "ffva1156" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "15" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../EPixHR10k2M_project.gen/sources_1/ip/TimingGth_fixedlat" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
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2 changes: 1 addition & 1 deletion LCLS-II/gthUltraScale+/ruckus.tcl
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Expand Up @@ -4,7 +4,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
if { $::env(VIVADO_VERSION) >= 2022.2} {
loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"

if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } {
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
} else {
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2 changes: 1 addition & 1 deletion LCLS-II/gthUltraScale/ruckus.tcl
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Expand Up @@ -5,7 +5,7 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } {

loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"

if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
if { [info exists ::env(LCLS_TIMING_GTH_XCI)] != 0 && $::env(LCLS_TIMING_GTH_XCI) == 1 } {
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
} else {
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53 changes: 29 additions & 24 deletions LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd
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Expand Up @@ -31,10 +31,11 @@ use unisim.vcomponents.all;
entity TimingGtCoreWrapper is
generic (
TPD_G : time := 1 ns;
SIMULATION_G : boolean := false;
DISABLE_TIME_GT_G : boolean := false;
EXTREF_G : boolean := false;
AXI_CLK_FREQ_G : real := 156.25e6;
AXIL_BASE_ADDR_G : slv(31 downto 0);
ADDR_BITS_G : positive := 22;
GTY_DRP_OFFSET_G : slv(31 downto 0) := x"00400000");
port (
-- AXI-Lite Port
Expand All @@ -45,8 +46,8 @@ entity TimingGtCoreWrapper is
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;
-- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableClk : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
stableRst : in sl; -- Unused in GTHE3, but used in GTHE4/GTYE4
-- GTY FPGA IO
gtRefClk : in sl;
gtRefClkDiv2 : in sl; -- Unused in GTYE3, but used in GTYE4
Expand All @@ -60,22 +61,23 @@ entity TimingGtCoreWrapper is
cpllRefClkSel : in slv(2 downto 0) := "001"; -- Set for "111" for gtgRefClk

-- Rx ports
rxControl : in TimingPhyControlType;
rxStatus : out TimingPhyStatusType;
rxUsrClkActive : in sl;
rxCdrStable : out sl;
rxUsrClk : in sl;
rxData : out slv(15 downto 0);
rxDataK : out slv(1 downto 0);
rxDispErr : out slv(1 downto 0);
rxDecErr : out slv(1 downto 0);
rxOutClk : out sl;
rxControl : in TimingPhyControlType;
rxStatus : out TimingPhyStatusType;
rxUsrClkActive : in sl;
rxCdrStable : out sl;
rxPmaRstDoneOut : out sl;
rxUsrClk : in sl;
rxData : out slv(15 downto 0);
rxDataK : out slv(1 downto 0);
rxDispErr : out slv(1 downto 0);
rxDecErr : out slv(1 downto 0);
rxOutClk : out sl;

-- Tx Ports
txControl : in TimingPhyControlType;
txStatus : out TimingPhyStatusType;
txUsrClk : in sl := '0';
txUsrClkActive : in sl := '0';
txUsrClk : in sl := '0';
txUsrClkActive : in sl := '0';
txData : in slv(15 downto 0) := (others => '0');
txDataK : in slv(1 downto 0) := (others => '0');
txOutClk : out sl;
Expand Down Expand Up @@ -233,11 +235,11 @@ architecture rtl of TimingGtCoreWrapper is
constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(1 downto 0) := (
0 => (
baseAddr => (AXIL_BASE_ADDR_G+x"00000000"),
addrBits => ADDR_BITS_G,
addrBits => 9,
connectivity => x"FFFF"),
1 => (
baseAddr => (AXIL_BASE_ADDR_G+GTY_DRP_OFFSET_G),
addrBits => ADDR_BITS_G,
addrBits => 12,
connectivity => x"FFFF"));

signal rxCtrl0Out : slv(15 downto 0) := (others => '0');
Expand Down Expand Up @@ -297,15 +299,18 @@ begin
mAxiReadMasters => axilReadMasters,
mAxiReadSlaves => axilReadSlaves);

U_AlignCheck : entity lcls_timing_core.GthRxAlignCheck
U_AlignCheck : entity surf.GtRxAlignCheck
generic map (
TPD_G => TPD_G,
GT_TYPE_G => "GTYE4",
DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
TPD_G => TPD_G,
SIMULATION_G => SIMULATION_G,
GT_TYPE_G => "GTYE4",
AXI_CLK_FREQ_G => AXI_CLK_FREQ_G,
DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr)
port map (
-- Clock Monitoring
txClk => txoutclkb,
rxClk => rxoutclkb,
rxClk => rxUsrClk,
refClk => axilClk, -- Could probably also be stableClk
-- GTH Status/Control Interface
resetIn => rxControl.reset,
resetDone => bypassdone,
Expand Down Expand Up @@ -448,7 +453,7 @@ begin
rxctrl2_out => open,
rxctrl3_out => rxCtrl3Out,
rxoutclk_out(0) => rxoutclk_out,
rxpmaresetdone_out => open,
rxpmaresetdone_out(0) => rxPmaRstDoneOut,
txoutclk_out(0) => txoutclk_out,
txpmaresetdone_out => open);

Expand Down Expand Up @@ -542,7 +547,7 @@ begin
rxctrl2_out => open,
rxctrl3_out => rxCtrl3Out,
rxoutclk_out(0) => rxoutclk_out,
rxpmaresetdone_out => open,
rxpmaresetdone_out(0) => rxPmaRstDoneOut,
txoutclk_out(0) => txoutclk_out,
txpmaresetdone_out => open);

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4 changes: 2 additions & 2 deletions LCLS-II/gtyUltraScale+/ruckus.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ if { [info exists ::env(TIMING_246MHz)] != 1 || $::env(TIMING_246MHz) == 0 } {

if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1} {

if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
if { [info exists ::env(LCLS_TIMING_GTY_XCI)] != 0 && $::env(LCLS_TIMING_GTY_XCI) == 1 } {
loadIpCore -path "${path}/TimingGty_extref.xci"
loadIpCore -path "${path}/TimingGty_fixedlat.xci"
puts "Loading XCI files for LCLS Timing"
Expand All @@ -26,7 +26,7 @@ if { $::env(VIVADO_VERSION) >= 2021.1 && [info exists ::env(TIMING_246MHz)] != 1

} elseif { $::env(VIVADO_VERSION) >= 2020.2 && [info exists ::env(TIMING_246MHz)] == 1 } {

if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
if { [info exists ::env(LCLS_TIMING_GTY_XCI)] != 0 && $::env(LCLS_TIMING_GTY_XCI) == 1 } {
loadIpCore -path "${path}/TimingGty_extref.xci"
loadIpCore -path "${path}/TimingGty_fixedlat.xci"
} else {
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2 changes: 1 addition & 1 deletion LICENSE.txt
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@

Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior
Copyright (c) 2025, The Board of Trustees of the Leland Stanford Junior
University, through SLAC National Accelerator Laboratory (subject to receipt
of any required approvals from the U.S. Dept. of Energy). All rights reserved.
Redistribution and use in source and binary forms, with or without
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2 changes: 1 addition & 1 deletion ruckus.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ if { [VersionCheck 2019.1 ] < 0 } {
# Check for submodule tagging
if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } {
if { [SubmoduleCheck {ruckus} {2.1.2} ] < 0 } {exit -1}
if { [SubmoduleCheck {surf} {2.8.0} ] < 0 } {exit -1}
if { [SubmoduleCheck {surf} {2.53.0} ] < 0 } {exit -1}
} else {
puts "\n\n*********************************************************"
puts "OVERRIDE_SUBMODULE_LOCKS != 0"
Expand Down

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