Update generated files

src/busctrl/perfsel0.rs

@@ -58,6 +58,7 @@ impl From<PERFSEL0_A> for u8 {
 impl crate::FieldSpec for PERFSEL0_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL0_A {}
 #[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL0_R = crate::FieldReader<PERFSEL0_A>;
 impl PERFSEL0_R {

src/busctrl/perfsel1.rs

@@ -58,6 +58,7 @@ impl From<PERFSEL1_A> for u8 {
 impl crate::FieldSpec for PERFSEL1_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL1_A {}
 #[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
 impl PERFSEL1_R {

src/busctrl/perfsel2.rs

@@ -58,6 +58,7 @@ impl From<PERFSEL2_A> for u8 {
 impl crate::FieldSpec for PERFSEL2_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL2_A {}
 #[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL2_R = crate::FieldReader<PERFSEL2_A>;
 impl PERFSEL2_R {

src/busctrl/perfsel3.rs

@@ -58,6 +58,7 @@ impl From<PERFSEL3_A> for u8 {
 impl crate::FieldSpec for PERFSEL3_A {
     type Ux = u8;
 }
+impl crate::IsEnum for PERFSEL3_A {}
 #[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
 pub type PERFSEL3_R = crate::FieldReader<PERFSEL3_A>;
 impl PERFSEL3_R {

src/clocks/clk_adc_ctrl.rs

@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_gpout0_ctrl.rs

@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_gpout1_ctrl.rs

@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_gpout2_ctrl.rs

@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_gpout3_ctrl.rs

@@ -40,6 +40,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_peri_ctrl.rs

@@ -32,6 +32,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_ref_ctrl.rs

@@ -24,6 +24,7 @@ impl From<SRC_A> for u8 {
 impl crate::FieldSpec for SRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for SRC_A {}
 #[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"]
 pub type SRC_R = crate::FieldReader<SRC_A>;
 impl SRC_R {
@@ -98,6 +99,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_rtc_ctrl.rs

@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_sys_ctrl.rs

@@ -85,6 +85,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/clk_usb_ctrl.rs

@@ -30,6 +30,7 @@ impl From<AUXSRC_A> for u8 {
 impl crate::FieldSpec for AUXSRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for AUXSRC_A {}
 #[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"]
 pub type AUXSRC_R = crate::FieldReader<AUXSRC_A>;
 impl AUXSRC_R {

src/clocks/fc0_src.rs

@@ -46,6 +46,7 @@ impl From<FC0_SRC_A> for u8 {
 impl crate::FieldSpec for FC0_SRC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for FC0_SRC_A {}
 #[doc = "Field `FC0_SRC` reader - "]
 pub type FC0_SRC_R = crate::FieldReader<FC0_SRC_A>;
 impl FC0_SRC_R {

src/dma/ch/ch_al1_ctrl.rs

@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]

src/dma/ch/ch_al2_ctrl.rs

@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]

src/dma/ch/ch_al3_ctrl.rs

@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]

src/dma/ch/ch_ctrl_trig.rs

@@ -38,6 +38,7 @@ impl From<DATA_SIZE_A> for u8 {
 impl crate::FieldSpec for DATA_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for DATA_SIZE_A {}
 #[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
 pub type DATA_SIZE_R = crate::FieldReader<DATA_SIZE_A>;
 impl DATA_SIZE_R {
@@ -126,6 +127,7 @@ impl From<RING_SIZE_A> for u8 {
 impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
+impl crate::IsEnum for RING_SIZE_A {}
 #[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.  
 
  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
@@ -280,6 +282,7 @@ impl From<TREQ_SEL_A> for u8 {
 impl crate::FieldSpec for TREQ_SEL_A {
     type Ux = u8;
 }
+impl crate::IsEnum for TREQ_SEL_A {}
 #[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal.  
  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).  
  0x0 to 0x3a -> select DREQ n as TREQ"]

src/dma/sniff_ctrl.rs

@@ -38,6 +38,7 @@ impl From<CALC_A> for u8 {
 impl crate::FieldSpec for CALC_A {
     type Ux = u8;
 }
+impl crate::IsEnum for CALC_A {}
 #[doc = "Field `CALC` reader - "]
 pub type CALC_R = crate::FieldReader<CALC_A>;
 impl CALC_R {

src/generic.rs

@@ -50,6 +50,8 @@ pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
     type Ux: Copy + PartialEq + From<Self>;
 }
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
 #[doc = " Trait implemented by readable registers to enable the `read` method."]
 #[doc = ""]
 #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
@@ -340,15 +342,13 @@ impl<FI> BitReader<FI> {
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
-#[doc = " Write field Proxy with unsafe `bits`"]
-pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
-#[doc = " Write field Proxy with safe `bits`"]
-pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
-impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
 {
     #[doc = " Field width"]
     pub const WIDTH: u8 = WI;
@@ -362,6 +362,13 @@ where
     pub const fn offset(&self) -> u8 {
         self.o
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes raw bits to the field"]
     #[doc = ""]
     #[doc = " # Safety"]
@@ -373,41 +380,29 @@ where
         self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
         self.w
     }
-    #[doc = " Writes `variant` to the field"]
-    #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        unsafe { self.bits(FI::Ux::from(variant)) }
-    }
 }
-impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
     REG::Ux: From<FI::Ux>,
 {
-    #[doc = " Field width"]
-    pub const WIDTH: u8 = WI;
-    #[doc = " Field width"]
-    #[inline(always)]
-    pub const fn width(&self) -> u8 {
-        WI
-    }
-    #[doc = " Field offset"]
-    #[inline(always)]
-    pub const fn offset(&self) -> u8 {
-        self.o
-    }
     #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
-        self.w
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes `variant` to the field"]
     #[inline(always)]
     pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        self.bits(FI::Ux::from(variant))
+        unsafe { self.bits(FI::Ux::from(variant)) }
     }
 }
 macro_rules! bit_proxy {

src/i2c0/ic_con.rs

@@ -95,6 +95,7 @@ impl From<SPEED_A> for u8 {
 impl crate::FieldSpec for SPEED_A {
     type Ux = u8;
 }
+impl crate::IsEnum for SPEED_A {}
 #[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.  
 
  This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.