hand-merged info.yaml, other files were automatic

.github/workflows/docs.yaml

@@ -18,7 +18,7 @@ jobs:
     - name: setup python
       uses: actions/setup-python@v4
       with:
-        python-version: '3.7.7'
+        python-version: '3.10'
     - run: pip install requests PyYAML
 
     # fetch the Verilog from Wokwi API

.github/workflows/gds.yaml

@@ -33,7 +33,7 @@ jobs:
     - name: setup python
       uses: actions/setup-python@v4
       with:
-        python-version: '3.7.7'
+        python-version: '3.10'
     - run: pip install requests PyYAML
 
     # fetch the Verilog from Wokwi API

configure.py

@@ -93,6 +93,13 @@ def check_docs(yaml):
             logging.error("missing value for {} in documentation".format(key))
             exit(1)
 
+    # if provided, check discord handle is valid
+    if len(yaml['documentation']['discord']):
+        parts = yaml['documentation']['discord'].split('#')
+        if len(parts) != 2 or len(parts[0]) == 0 or not re.match('^[0-9]{4}$', parts[1]):
+            logging.error(f'Invalid format for discord username')
+            exit(1)
+
 
 def get_top_module(yaml):
     wokwi_id = int(yaml['project']['wokwi_id'])
@@ -149,4 +156,5 @@ def get_stats():
         config = load_yaml(args.yaml)
         source_files = get_project_source(config)
         top_module = get_top_module(config)
+        assert top_module != 'top'
         write_user_config(top_module, source_files)

info.yaml

@@ -13,7 +13,7 @@ project:
 # Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
 #
 # This info will be automatically collected and used to make a datasheet for the chip.
-documentation: 
+documentation:
   author:       "Rolf Widenfelt"      # Your name
   discord:      "?"      # Your discord handle
   title:        "4-bit badge ALU"      # Project title
@@ -23,7 +23,7 @@ documentation:
   external_hw:  ""      # Describe any external hardware needed
   language:     "verilog" # other examples include Verilog, Amaranth, VHDL, etc
   doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
-  clock_hz:     0       # Clock frequency in Hz (if required)
+  clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
   picture:      ""      # relative path to a picture in your repository
   inputs:               # input pins 7-0 (e.g. clk is pin 7)
     - clk

src/cells.v

@@ -93,9 +93,9 @@ module dffsr_cell (
 
     always @(posedge clk or posedge s or posedge r) begin
         if (r)
-            q <= '0;
+            q <= 0;
         else if (s)
-            q <= '1;
+            q <= 1;
         else
             q <= d;
     end

src/config.tcl

@@ -29,8 +29,8 @@ set ::env(BOTTOM_MARGIN_MULT) 2
 
 # absolute die size
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 90 120"
-set ::env(FP_CORE_UTIL) 45
+set ::env(DIE_AREA) "0 0 150 170"
+set ::env(FP_CORE_UTIL) 55
 set ::env(PL_BASIC_PLACEMENT) {1}
 
 set ::env(FP_IO_HLENGTH) 2
@@ -45,8 +45,13 @@ set ::env(DECAP_CELL) "\
     sky130_ef_sc_hd__decap_12"
 
 # clock
-set ::env(CLOCK_TREE_SYNTH) 0
-set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_TREE_SYNTH) 1
+set ::env(CLOCK_PERIOD) "100000"
+set ::env(CLOCK_PORT) {io_in[0]}
+
+# hold/slack margin
+# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 
+# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 
 
 # don't use power rings or met5
 set ::env(DESIGN_IS_CORE) 0