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Merge branch 'master' into zfa
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@robehn
robehn committed Jan 22, 2025
2 parents 2df7460 + fb43849 commit 7e2c9d7
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Showing 8 changed files with 485 additions and 324 deletions.
769 changes: 462 additions & 307 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/assembler_riscv.inline.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ inline bool Assembler::is_simm13(int64_t x) { return is_simm(x, 13); }
inline bool Assembler::is_simm18(int64_t x) { return is_simm(x, 18); }
inline bool Assembler::is_simm21(int64_t x) { return is_simm(x, 21); }

inline bool Assembler::is_uimm2(uint64_t x) { return is_uimm(x, 2); }
inline bool Assembler::is_uimm3(uint64_t x) { return is_uimm(x, 3); }
inline bool Assembler::is_uimm5(uint64_t x) { return is_uimm(x, 5); }
inline bool Assembler::is_uimm6(uint64_t x) { return is_uimm(x, 6); }
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6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
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Expand Up @@ -2058,7 +2058,7 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
is_double ? fclass_d(t1, src2)
: fclass_s(t1, src2);
orr(t0, t0, t1);
andi(t0, t0, fclass_mask::nan); // if src1 or src2 is quiet or signaling NaN then return NaN
andi(t0, t0, FClassBits::nan); // if src1 or src2 is quiet or signaling NaN then return NaN
beqz(t0, Compare);
is_double ? fadd_d(dst, src1, src2)
: fadd_s(dst, src1, src2);
Expand Down Expand Up @@ -2152,7 +2152,7 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister one, bool is_
: fclass_s(t0, dst);

// check if input is -0, +0, signaling NaN or quiet NaN
andi(t0, t0, fclass_mask::zero | fclass_mask::nan);
andi(t0, t0, FClassBits::zero | FClassBits::nan);

bnez(t0, done);

Expand Down Expand Up @@ -2368,7 +2368,7 @@ void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, Basi

// check if input is -0, +0, signaling NaN or quiet NaN
vfclass_v(v0, dst);
mv(t0, fclass_mask::zero | fclass_mask::nan);
mv(t0, FClassBits::zero | FClassBits::nan);
vand_vx(v0, v0, t0);
vmseq_vi(v0, v0, 0);

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1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/globals_riscv.hpp
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Expand Up @@ -105,6 +105,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseZbs, false, DIAGNOSTIC, "Use Zbs instructions") \
product(bool, UseZfa, false, EXPERIMENTAL, "Use Zfa instructions") \
product(bool, UseZfh, false, DIAGNOSTIC, "Use Zfh instructions") \
product(bool, UseZfhmin, false, DIAGNOSTIC, "Use Zfhmin instructions") \
product(bool, UseZacas, false, EXPERIMENTAL, "Use Zacas instructions") \
product(bool, UseZcb, false, EXPERIMENTAL, "Use Zcb instructions") \
product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \
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16 changes: 7 additions & 9 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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Expand Up @@ -2599,17 +2599,15 @@ bool MacroAssembler::can_fp_imm_load(float imm) {
if (f_bits == 0) {
return true;
}
int dummy;
return can_zfa_zli_float(imm, &dummy);
return can_zfa_zli_float(imm);
}

bool MacroAssembler::can_dp_imm_load(double imm) {
julong d_bits = julong_cast(imm);
if (d_bits == 0) {
return true;
}
int dummy;
return can_zfa_zli_double(imm, &dummy);
return can_zfa_zli_double(imm);
}

void MacroAssembler::fli_s(FloatRegister Rd, float imm) {
Expand All @@ -2618,8 +2616,8 @@ void MacroAssembler::fli_s(FloatRegister Rd, float imm) {
fmv_w_x(Rd, zr);
return;
}
int Rs = -1;
can_zfa_zli_float(imm, &Rs);
int Rs = zfa_zli_lookup_float(f_bits);
assert(Rs != -1, "Must be");
_fli_s(Rd, Rs);
}

Expand All @@ -2629,8 +2627,8 @@ void MacroAssembler::fli_d(FloatRegister Rd, double imm) {
fmv_d_x(Rd, zr);
return;
}
int Rs = -1;
can_zfa_zli_double(imm, &Rs);
int Rs = zfa_zli_lookup_double(d_bits);
assert(Rs != -1, "Must be");
_fli_d(Rd, Rs);
}

Expand Down Expand Up @@ -5927,7 +5925,7 @@ void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src, Register t
fclass_##FLOATSIG(tmp, src); \
mv(dst, zr); \
/* check if src is NaN */ \
andi(tmp, tmp, fclass_mask::nan); \
andi(tmp, tmp, FClassBits::nan); \
bnez(tmp, done); \
FLOATCVT(dst, src); \
bind(done); \
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10 changes: 5 additions & 5 deletions src/hotspot/cpu/riscv/riscv.ad
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Expand Up @@ -1918,7 +1918,7 @@ bool Matcher::match_rule_supported(int opcode) {

case Op_ConvHF2F:
case Op_ConvF2HF:
return UseZfh;
return UseZfh || UseZfhmin;
}

return true; // Per default match rules are supported.
Expand Down Expand Up @@ -7356,7 +7356,7 @@ instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
format %{ "isInfinite $dst, $src" %}
ins_encode %{
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}

Expand All @@ -7371,7 +7371,7 @@ instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
format %{ "isInfinite $dst, $src" %}
ins_encode %{
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::inf);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}

Expand All @@ -7386,7 +7386,7 @@ instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
format %{ "isFinite $dst, $src" %}
ins_encode %{
__ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}

Expand All @@ -7401,7 +7401,7 @@ instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
format %{ "isFinite $dst, $src" %}
ins_encode %{
__ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_mask::finite);
__ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
__ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
%}

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3 changes: 3 additions & 0 deletions src/hotspot/cpu/riscv/vm_version_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -115,6 +115,7 @@ class VM_Version : public Abstract_VM_Version {
// Zbs Single-bit instructions
//
// Zfh Half-Precision Floating-Point instructions
// Zfhmin Minimal Half-Precision Floating-Point instructions
//
// Zicond Conditional operations
//
Expand Down Expand Up @@ -158,6 +159,7 @@ class VM_Version : public Abstract_VM_Version {
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZcb)) \
decl(ext_Zfa , "Zfa" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfa)) \
decl(ext_Zfh , "Zfh" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfh)) \
decl(ext_Zfhmin , "Zfhmin" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfhmin)) \
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zicntr , "Zicntr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
Expand Down Expand Up @@ -226,6 +228,7 @@ class VM_Version : public Abstract_VM_Version {
RV_ENABLE_EXTENSION(UseZbs) \
RV_ENABLE_EXTENSION(UseZcb) \
RV_ENABLE_EXTENSION(UseZfa) \
RV_ENABLE_EXTENSION(UseZfhmin) \
RV_ENABLE_EXTENSION(UseZic64b) \
RV_ENABLE_EXTENSION(UseZicbom) \
RV_ENABLE_EXTENSION(UseZicbop) \
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3 changes: 3 additions & 0 deletions src/hotspot/os_cpu/linux_riscv/riscv_hwprobe.cpp
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Expand Up @@ -177,6 +177,9 @@ void RiscvHwprobe::add_features_from_query_result() {
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZFH)) {
VM_Version::ext_Zfh.enable_feature();
}
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZFHMIN)) {
VM_Version::ext_Zfhmin.enable_feature();
}
if (is_set(RISCV_HWPROBE_KEY_IMA_EXT_0, RISCV_HWPROBE_EXT_ZVBC)) {
VM_Version::ext_Zvbc.enable_feature();
}
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