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Fixed reg names
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@robehn
robehn committed Feb 21, 2025
1 parent 16033ea commit 498e730
Showing 1 changed file with 86 additions and 111 deletions.
197 changes: 86 additions & 111 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -627,13 +627,13 @@ class Assembler : public AbstractAssembler {

// Load/store register (all modes)
#define INSN(NAME, op, funct3) \
void NAME(Register Rd, Register Rs, const int32_t offset) { \
void NAME(Register Rd, Register Rs1, const int32_t offset) { \
guarantee(is_simm12(offset), "offset is invalid."); \
unsigned insn = 0; \
int32_t val = offset & 0xfff; \
patch((address)&insn, 6, 0, op); \
patch((address)&insn, 14, 12, funct3); \
patch_reg((address)&insn, 15, Rs); \
patch_reg((address)&insn, 15, Rs1); \
patch_reg((address)&insn, 7, Rd); \
patch((address)&insn, 31, 20, val); \
emit(insn); \
Expand Down Expand Up @@ -679,23 +679,23 @@ class Assembler : public AbstractAssembler {
#undef INSN

#define INSN(NAME, REGISTER, op, funct3) \
void NAME(REGISTER Rs1, Register Rs2, const int32_t offset) { \
void NAME(REGISTER Rs2_src, Register Rs1_base, const int32_t offset) { \
guarantee(is_simm12(offset), "offset is invalid."); \
unsigned insn = 0; \
uint32_t val = offset & 0xfff; \
uint32_t low = val & 0x1f; \
uint32_t high = (val >> 5) & 0x7f; \
patch((address)&insn, 6, 0, op); \
patch((address)&insn, 14, 12, funct3); \
patch_reg((address)&insn, 15, Rs2); \
patch_reg((address)&insn, 20, Rs1); \
patch_reg((address)&insn, 15, Rs1_base); \
patch_reg((address)&insn, 20, Rs2_src); \
patch((address)&insn, 11, 7, low); \
patch((address)&insn, 31, 25, high); \
emit(insn); \
} \

INSN(_sb, Register, 0b0100011, 0b000);
INSN(_sh, Register, 0b0100011, 0b001);
INSN(_sb, Register, 0b0100011, 0b000);
INSN(_sh, Register, 0b0100011, 0b001);
INSN(_sw, Register, 0b0100011, 0b010);
INSN(_sd, Register, 0b0100011, 0b011);
INSN(fsw, FloatRegister, 0b0100111, 0b010);
Expand Down Expand Up @@ -757,13 +757,13 @@ class Assembler : public AbstractAssembler {
}

// Format I-type
void _jalr(Register Rd, Register Rs, const int32_t offset) {
void _jalr(Register Rd, Register Rs1, const int32_t offset) {
guarantee(is_simm12(offset), "offset is invalid.");
unsigned insn = 0;
patch((address)&insn, 6, 0, 0b1100111);
patch_reg((address)&insn, 7, Rd);
patch((address)&insn, 14, 12, 0b000);
patch_reg((address)&insn, 15, Rs);
patch_reg((address)&insn, 15, Rs1);
int32_t val = offset & 0xfff;
patch((address)&insn, 31, 20, val);
emit(insn);
Expand Down Expand Up @@ -874,18 +874,18 @@ enum operand_size { int8, int16, int32, uint32, int64 };

#undef INSN

#define INSN(NAME, op, funct3, funct7) \
void NAME(Register Rd, Register Rs1, Register Rs2, Aqrl memory_order = relaxed) { \
unsigned insn = 0; \
uint32_t val = memory_order & 0x3; \
patch((address)&insn, 6, 0, op); \
patch((address)&insn, 14, 12, funct3); \
patch_reg((address)&insn, 7, Rd); \
patch_reg((address)&insn, 15, Rs2); \
patch_reg((address)&insn, 20, Rs1); \
patch((address)&insn, 31, 27, funct7); \
patch((address)&insn, 26, 25, val); \
emit(insn); \
#define INSN(NAME, op, funct3, funct7) \
void NAME(Register Rd, Register Rs2_src, Register Rs1_addr, Aqrl memory_order = relaxed) { \
unsigned insn = 0; \
uint32_t val = memory_order & 0x3; \
patch((address)&insn, 6, 0, op); \
patch((address)&insn, 14, 12, funct3); \
patch_reg((address)&insn, 7, Rd); \
patch_reg((address)&insn, 15, Rs1_addr); \
patch_reg((address)&insn, 20, Rs2_src); \
patch((address)&insn, 31, 27, funct7); \
patch((address)&insn, 26, 25, val); \
emit(insn); \
}

INSN(sc_w, 0b0101111, 0b010, 0b00011);
Expand Down Expand Up @@ -1301,15 +1301,15 @@ enum operand_size { int8, int16, int32, uint32, int64 };
static constexpr unsigned int OP_LOAD_FP = 0b0000111;

template <int8_t FpWidth>
void fp_load(FloatRegister Rd, Register Rs, const int32_t offset) {
void fp_load(FloatRegister Rd, Register Rs1, const int32_t offset) {
guarantee(is_uimm3(FpWidth), "Rounding mode is out of validity");
guarantee(is_simm12(offset), "offset is invalid.");
unsigned insn = 0;
uint32_t val = offset & 0xfff;
patch((address)&insn, 6, 0, OP_LOAD_FP);
patch_reg((address)&insn, 7, Rd);
patch((address)&insn, 14, 12, FpWidth);
patch_reg((address)&insn, 15, Rs);
patch_reg((address)&insn, 15, Rs1);
patch((address)&insn, 31, 20, val);
emit(insn);
}
Expand Down Expand Up @@ -2999,33 +2999,28 @@ enum Nf {
private:
// some helper functions
#define FUNC(NAME, funct3, bits) \
bool NAME(Register rs1, Register rd_rs2, int32_t imm12, bool ld) { \
return rs1 == sp && \
bool NAME(Register Rs1, Register Rd_Rs2, int32_t imm12, bool ld) { \
return Rs1 == sp && \
is_uimm(imm12, bits) && \
(intx(imm12) & funct3) == 0x0 && \
(!ld || rd_rs2 != x0); \
(!ld || Rd_Rs2 != x0); \
} \

FUNC(is_c_ldsdsp, 0b111, 9);
FUNC(is_c_lwswsp, 0b011, 8);

#undef FUNC

#define FUNC(NAME, funct3, bits) \
bool NAME(Register rs1, int32_t imm12) { \
return rs1 == sp && \
is_uimm(imm12, bits) && \
(intx(imm12) & funct3) == 0x0; \
} \

FUNC(is_c_fldsdsp, 0b111, 9);

#undef FUNC
bool is_c_fldsdsp(Register Rs1_base, int32_t imm12) {
return Rs1_base == sp &&
is_uimm(imm12, 9) &&
(intx(imm12) & 0b111) == 0x0;
}

#define FUNC(NAME, REG_TYPE, funct3, bits) \
bool NAME(Register rs1, REG_TYPE rd_rs2, int32_t imm12) { \
return rs1->is_compressed_valid() && \
rd_rs2->is_compressed_valid() && \
bool NAME(Register Rs1, REG_TYPE Rd_Rs2, int32_t imm12) { \
return Rs1->is_compressed_valid() && \
Rd_Rs2->is_compressed_valid() && \
is_uimm(imm12, bits) && \
(intx(imm12) & funct3) == 0x0; \
} \
Expand Down Expand Up @@ -3093,85 +3088,65 @@ enum Nf {
#undef INSN

// --------------------------
#define INSN(NAME) \
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
/* fld -> c.fldsp/c.fld */ \
if (do_compress()) { \
if (is_c_fldsdsp(Rs, offset)) { \
c_fldsp(Rd, offset); \
return; \
} else if (is_c_fldsd(Rs, Rd, offset)) { \
c_fld(Rd, Rs, offset); \
return; \
} \
} \
_fld(Rd, Rs, offset); \
void fld(FloatRegister Rs2_src, Register Rs1_base, const int32_t offset) {
/* fld -> c.fldsp/c.fld */
if (do_compress()) {
if (is_c_fldsdsp(Rs1_base, offset)) {
c_fldsp(Rs2_src, offset);
return;
} else if (is_c_fldsd(Rs1_base, Rs2_src, offset)) {
c_fld(Rs2_src, Rs1_base, offset);
return;
}
}
_fld(Rs2_src, Rs1_base, offset);
}

INSN(fld);

#undef INSN

// --------------------------
#define INSN(NAME) \
void NAME(Register Rd, Register Rs, const int32_t offset) { \
/* sd -> c.sdsp/c.sd */ \
if (do_compress()) { \
if (is_c_ldsdsp(Rs, Rd, offset, false)) { \
c_sdsp(Rd, offset); \
return; \
} else if (is_c_ldsd(Rs, Rd, offset)) { \
c_sd(Rd, Rs, offset); \
return; \
} \
} \
_sd(Rd, Rs, offset); \
void sd(Register Rs2_src, Register Rs1_base, const int32_t offset) {
/* sd -> c.sdsp/c.sd */
if (do_compress()) {
if (is_c_ldsdsp(Rs1_base, Rs2_src, offset, false)) {
c_sdsp(Rs2_src, offset);
return;
} else if (is_c_ldsd(Rs1_base, Rs2_src, offset)) {
c_sd(Rs2_src, Rs1_base, offset);
return;
}
}
_sd(Rs2_src, Rs1_base, offset);
}

INSN(sd);

#undef INSN

// --------------------------
#define INSN(NAME) \
void NAME(Register Rd, Register Rs, const int32_t offset) { \
/* sw -> c.swsp/c.sw */ \
if (do_compress()) { \
if (is_c_lwswsp(Rs, Rd, offset, false)) { \
c_swsp(Rd, offset); \
return; \
} else if (is_c_lwsw(Rs, Rd, offset)) { \
c_sw(Rd, Rs, offset); \
return; \
} \
} \
_sw(Rd, Rs, offset); \
void sw(Register Rd, Register Rs, const int32_t offset) {
/* sw -> c.swsp/c.sw */
if (do_compress()) {
if (is_c_lwswsp(Rs, Rd, offset, false)) {
c_swsp(Rd, offset);
return;
} else if (is_c_lwsw(Rs, Rd, offset)) {
c_sw(Rd, Rs, offset);
return;
}
}
_sw(Rd, Rs, offset);
}

INSN(sw);

#undef INSN

// --------------------------
#define INSN(NAME) \
void NAME(FloatRegister Rd, Register Rs, const int32_t offset) { \
/* fsd -> c.fsdsp/c.fsd */ \
if (do_compress()) { \
if (is_c_fldsdsp(Rs, offset)) { \
c_fsdsp(Rd, offset); \
return; \
} else if (is_c_fldsd(Rs, Rd, offset)) { \
c_fsd(Rd, Rs, offset); \
return; \
} \
} \
_fsd(Rd, Rs, offset); \
void fsd(FloatRegister Rs2_src, Register Rs1_base, const int32_t offset) {
/* fsd -> c.fsdsp/c.fsd */
if (do_compress()) {
if (is_c_fldsdsp(Rs1_base, offset)) {
c_fsdsp(Rs2_src, offset);
return;
} else if (is_c_fldsd(Rs1_base, Rs2_src, offset)) {
c_fsd(Rs2_src, Rs1_base, offset);
return;
}
}
_fsd(Rs2_src, Rs1_base, offset);
}

INSN(fsd);

#undef INSN

// --------------------------
// Unconditional branch instructions
// --------------------------
Expand Down Expand Up @@ -3428,13 +3403,13 @@ enum Nf {

public:
// Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd.
void czero_eqz(Register rd, Register rs1_value, Register rs2_condition) {
czero<CZERO_EQZ>(rd, rs1_value, rs2_condition);
void czero_eqz(Register Rd, Register Rs1_value, Register Rs2_condition) {
czero<CZERO_EQZ>(Rd, Rs1_value, Rs2_condition);
}

// Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd.
void czero_nez(Register rd, Register rs1_value, Register rs2_condition) {
czero<CZERO_NEZ>(rd, rs1_value, rs2_condition);
void czero_nez(Register Rd, Register Rs1_value, Register Rs2_condition) {
czero<CZERO_NEZ>(Rd, Rs1_value, Rs2_condition);
}

// -------------- ZCB Instruction Definitions --------------
Expand Down

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