gtest

robehn · Nov 25, 2024 · 40da263 · 40da263
1 parent 808e124
commit 40da263
Showing 1 changed file with 52 additions and 27 deletions.
diff --git a/test/hotspot/gtest/riscv/test_assembler_riscv.cpp b/test/hotspot/gtest/riscv/test_assembler_riscv.cpp
@@ -31,44 +31,69 @@
 #include "memory/resourceArea.hpp"
 #include "unittest.hpp"
 
-typedef uint64_t (*zicond_eq)(int64_t cmp1, int64_t cmp2, int64_t dst, int64_t src);
+typedef int64_t (*zicond_func)(int64_t cmp1, int64_t cmp2, int64_t dst, int64_t src);
+typedef void (MacroAssembler::*cmov_func)(Register cmp1, Register cmp2, Register dst, Register src);
 
 class CmovTester {
  public:
-  template <typename FUNC>
-  static void test(FUNC &f) {
+  static void test(cmov_func func, int64_t a0, int64_t a1, int64_t a2, int64_t a3, int64_t result) {
     BufferBlob* bb = BufferBlob::create("riscvTest", 500000);
     CodeBuffer code(bb);
     MacroAssembler _masm(&code);
-    f(_masm);
+    #define __ _masm.
+    address entry = __ pc();
+    ((&_masm)->*func)(c_rarg0, c_rarg1, c_rarg2, c_rarg3);
+    __ mv(c_rarg0, c_rarg2);
+    __ ret();
+    #undef __
+    int64_t ret = ((zicond_func)entry)(a0, a1, a2, a3);
+    ASSERT_EQ(ret, result);
     BufferBlob::free(bb);
   }
 };
+
+TEST_VM(Instruction, Cmov) {
+  // If UseZicond is hwprobe settable, execute gtest with: 
+  // -XX:+UnlockExperimentalVMOptions -XX:+UseZicond
+  //
+  // If 42(a0) eq 42(a1): assign dest(a2/66) the src(a3/77), expect result: 77
+  CmovTester::test(&MacroAssembler::cmov_eq, 42, 42, 66, 77, 77);
+  // If 41(a0) eq 42(a1): assign dest(a2/66) the src(a3/77), expect result: 66
+  CmovTester::test(&MacroAssembler::cmov_eq, 41, 42, 66, 77, 66);
 
-static void cmov_eq_true(MacroAssembler& _masm) {
-  #define __ _masm.
-  address entry = __ pc();
-  __ cmov_eq(c_rarg0, c_rarg1, c_rarg2, c_rarg3);
-  __ mv(c_rarg0, c_rarg2);
-  __ ret();
-  #undef __
-  uint64_t ret = ((zicond_eq)entry)(88, 88, 66, 77);
-  ASSERT_EQ(ret, 77ul);
-}
+  CmovTester::test(&MacroAssembler::cmov_ne, 41, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_ne, 42, 42, 66, 77, 66);
 
-static void cmov_eq_false(MacroAssembler& _masm) {
-  #define __ _masm.
-  address entry = __ pc();
-  __ cmov_eq(c_rarg0, c_rarg1, c_rarg2, c_rarg3);
-  __ mv(c_rarg0, c_rarg2);
-  __ ret();
-  #undef __
-  uint64_t ret = ((zicond_eq)entry)(88, 87, 66, 77);
-  ASSERT_EQ(ret, 66ul);
-}
+  CmovTester::test(&MacroAssembler::cmov_le, 41, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_le, 42, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_le, 42, -1, 66, 77, 66);
 
-TEST_VM(Instruction, Cmov) {
-  CmovTester::test(cmov_eq_true);
-  CmovTester::test(cmov_eq_false);
+  CmovTester::test(&MacroAssembler::cmov_leu, 41, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_leu, 42, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_leu, -1, 42, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_ge, 43, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_ge, 42, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_ge, -1, 42, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_geu, 43, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_geu, 42, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_geu, 42, -1, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_lt, 41, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_lt, 42, 42, 66, 77, 66);
+  CmovTester::test(&MacroAssembler::cmov_lt, 42, -1, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_ltu, 41, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_ltu, 42, 42, 66, 77, 66);
+  CmovTester::test(&MacroAssembler::cmov_ltu, -1, 42, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_gt, 43, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_gt, 42, 42, 66, 77, 66);
+  CmovTester::test(&MacroAssembler::cmov_gt, -1, 42, 66, 77, 66);
+
+  CmovTester::test(&MacroAssembler::cmov_gtu, 43, 42, 66, 77, 77);
+  CmovTester::test(&MacroAssembler::cmov_gtu, 42, 42, 66, 77, 66);
+  CmovTester::test(&MacroAssembler::cmov_gtu, 42, -1, 66, 77, 66);
 }
 #endif  // RISCV