Fix rw overlap check by only performing it on x register.

handwritten/hexagon_il_c/functions.c

@@ -624,6 +624,37 @@ static inline bool read_cond_faulty(RzILOpPure *low_val, RzILOpPure *high_val, u
 	return false;
 }
 
+/**
+ * \brief Checks for rw registers (e.g. Rx) if reads and writes overlap.
+ *
+ * \param pkt The packet of the current instruction.
+ * \param op The operand to check.
+ * \param reg_num The number of the register to check.
+ *
+ * \return true If the register is a "x" register and it was read and written before.
+ * \return false Otherwise.
+ */
+static bool x_reg_rw_overlap(const HexPkt *pkt, const HexOp *op, ut32 reg_num) {
+	switch(op->class) {
+	default:
+		rz_warn_if_reached();
+		RZ_LOG_WARN("Checking rw overlap of class %d not implemented yet.", op->class);
+		return false;
+	case HEX_REG_CLASS_INT_REGS:
+	case HEX_REG_CLASS_INT_REGS_LOW8:
+	case HEX_REG_CLASS_GENERAL_SUB_REGS:
+	case HEX_REG_CLASS_DOUBLE_REGS:
+	case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
+		return (pkt->il_op_stats.gpr_written & (1 << reg_num)) && (pkt->il_op_stats.gpr_read & (1 << reg_num)) && op->isa_id == 'x';
+	case HEX_REG_CLASS_MOD_REGS:
+	case HEX_REG_CLASS_CTR_REGS:
+	case HEX_REG_CLASS_CTR_REGS64:
+		return (pkt->il_op_stats.ctr_written & (1 << reg_num)) && (pkt->il_op_stats.ctr_read & (1 << reg_num)) && op->isa_id == 'x';
+	case HEX_REG_CLASS_PRED_REGS:
+		return (pkt->il_op_stats.pred_written & (1 << reg_num)) && (pkt->il_op_stats.pred_read & (1 << reg_num)) && op->isa_id == 'x';
+	}
+}
+
 /**
  * \brief Reads a value from the register specified in \p op and logs the read.
  * If the register is a double register, each of its sub-registers are read separately.
@@ -651,7 +682,7 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 		return NULL;
 	case HEX_REG_CLASS_DOUBLE_REGS:
 	case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
-		if ((pkt->il_op_stats.gpr_written & (1 << (reg_num + 1))) && (pkt->il_op_stats.gpr_read & (1 << (reg_num + 1)))) {
+		if (x_reg_rw_overlap(pkt, op, reg_num + 1)) {
 			// If read and writes overlap, return the new register for each read.
 			tmp_reg = true;
 		}
@@ -662,15 +693,15 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 	case HEX_REG_CLASS_INT_REGS:
 	case HEX_REG_CLASS_INT_REGS_LOW8:
 	case HEX_REG_CLASS_GENERAL_SUB_REGS:
-		if ((pkt->il_op_stats.gpr_written & (1 << reg_num)) && (pkt->il_op_stats.gpr_read & (1 << reg_num))) {
+		if (x_reg_rw_overlap(pkt, op, reg_num)) {
 			// If read and writes overlap, return the new register for each read.
 			tmp_reg = true;
 		}
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num, false, tmp_reg, true);
 		low_val = VARG(low_name);
 		break;
 	case HEX_REG_CLASS_CTR_REGS64:
-		if ((pkt->il_op_stats.ctr_written & (1 << (reg_num + 1))) && (pkt->il_op_stats.ctr_read & (1 << (reg_num + 1)))) {
+		if (x_reg_rw_overlap(pkt, op, reg_num + 1)) {
 			// If read and writes overlap, return the new register for each read.
 			tmp_reg = true;
 		}
@@ -685,7 +716,7 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 		// fallthrough
 	case HEX_REG_CLASS_MOD_REGS:
 	case HEX_REG_CLASS_CTR_REGS:
-		if ((pkt->il_op_stats.ctr_written & (1 << reg_num)) && (pkt->il_op_stats.ctr_read & (1 << reg_num))) {
+		if (x_reg_rw_overlap(pkt, op, reg_num)) {
 			// If read and writes overlap, return the new register for each read.
 			tmp_reg = true;
 		}
@@ -711,7 +742,7 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 		}
 		break;
 	case HEX_REG_CLASS_PRED_REGS:
-		if ((pkt->il_op_stats.pred_written & (1 << reg_num)) && (pkt->il_op_stats.pred_read & (1 << reg_num))) {
+		if (x_reg_rw_overlap(pkt, op, reg_num)) {
 			// If read and writes overlap, return the new register for each read.
 			tmp_reg = true;
 		}