Compilation, build error and test fixes [Capstone to Zydis]

.gitignore

@@ -134,7 +134,6 @@ subprojects/xz-*/
 subprojects/zstd-*/
 subprojects/softflo*/
 subprojects/zydis/
-subprojects/zycore.wrap
 dist/windows/Output
 # Core files generated by OpenBSD
 *.core

librz/arch/isa/x86/common.c

@@ -730,7 +730,7 @@ RZ_IPI RzILOpEffect *x86_il_set_mem_bits(X86Mem mem, RZ_OWN RZ_NONNULL RzILOpPur
  * \param op
  * \param analysis_bits bitness
  */
-RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, X86ILIns *ins) {
+RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, const X86ILIns *ins) {
 	switch (op.type) {
 	// case X86_OP_INVALID:
 	//	if (implicit_size) {
@@ -742,7 +742,7 @@ RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc,
 		return x86_il_get_reg_bits(op.reg.value, analysis_bits, pc);
 	case ZYDIS_OPERAND_TYPE_IMMEDIATE:
 		/* Immediate values are always sign extended */
-		return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, imm_value(op, pc, ins->ins_size));
+		return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, imm_value(op, pc));
 	case ZYDIS_OPERAND_TYPE_MEMORY:
 		return LOADW((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc));
 	default:
@@ -805,7 +805,7 @@ RZ_IPI RzILOpBool *x86_il_is_add_carry(RZ_OWN RZ_NONNULL RzILOpPure *res, RZ_OWN
 	RzILOpBool *xr = AND(DUP(xmsb), DUP(nres));
 
 	// bit = xy | ry | xr
-	RzILOpBool *or = OR(xy, ry);
+	RzILOpBool * or = OR(xy, ry);
 	or = OR(or, xr);
 
 	return or ;
@@ -836,7 +836,7 @@ RZ_IPI RzILOpBool *x86_il_is_sub_borrow(RZ_OWN RZ_NONNULL RzILOpPure *res, RZ_OW
 	RzILOpBool *rnx = AND(DUP(resmsb), DUP(nx));
 
 	// bit = nxy | rny | rnx
-	RzILOpBool *or = OR(nxy, rny);
+	RzILOpBool * or = OR(nxy, rny);
 	or = OR(or, rnx);
 
 	return or ;
@@ -862,7 +862,7 @@ RZ_IPI RzILOpBool *x86_il_is_add_overflow(RZ_OWN RZ_NONNULL RzILOpPure *res, RZ_
 	// res & !x & !y
 	RzILOpBool *rnxny = AND(AND(DUP(resmsb), INV(DUP(xmsb))), INV(DUP(ymsb)));
 	// or = nrxy | rnxny
-	RzILOpBool *or = OR(nrxy, rnxny);
+	RzILOpBool * or = OR(nrxy, rnxny);
 
 	return or ;
 }
@@ -887,7 +887,7 @@ RZ_IPI RzILOpBool *x86_il_is_sub_underflow(RZ_OWN RZ_NONNULL RzILOpPure *res, RZ
 	// res & !x & y
 	RzILOpBool *rnxy = AND(AND(DUP(resmsb), INV(DUP(xmsb))), DUP(ymsb));
 	// or = nrxny | rnxy
-	RzILOpBool *or = OR(nrxny, rnxy);
+	RzILOpBool * or = OR(nrxny, rnxy);
 
 	return or ;
 }
@@ -1478,7 +1478,7 @@ RZ_IPI RzILOpPure *x86_il_get_floating_operand_bits(X86Op op, int bits, ut64 pc)
 		if (x86_il_is_st_reg(op.reg.value)) {
 			return x86_il_get_st_reg(op.reg.value);
 		} else {
-			RZ_LOG_ERROR("x86: RzIL: Invalid register passed as a floating point operand: %d\n", op.reg);
+			RZ_LOG_ERROR("x86: RzIL: Invalid register passed as a floating point operand: %d\n", op.reg.value);
 		}
 		break;
 	case ZYDIS_OPERAND_TYPE_MEMORY:

librz/arch/isa/x86/common.h

@@ -88,7 +88,7 @@ extern const char *x86_eflags_registers[X86_EFLAGS_ENDING];
 RZ_IPI RzILOpPure *x86_il_get_reg_bits(X86Reg reg, int bits, uint64_t pc);
 RZ_IPI RzILOpEffect *x86_il_set_reg_bits(X86Reg reg, RZ_OWN RZ_NONNULL RzILOpPure *val, int bits);
 
-RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, X86ILIns *ins);
+RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, const X86ILIns *ins);
 RZ_IPI RzILOpEffect *x86_il_set_operand_bits(X86Op op, RZ_OWN RZ_NONNULL RzILOpPure *val, int bits, ut64 pc);
 
 RZ_IPI RzILOpPure *x86_il_get_memaddr_bits(X86Mem mem, int bits, ut64 pc);

librz/arch/isa/x86/il_ops.inc

@@ -343,14 +343,14 @@ RzILOpEffect *x86_il_cmp_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analys
 
 		X86Mem src_mem1 = {
 			.base = mem_reg1,
-			.disp = 0,
+			.disp = { 0 },
 			.index = ZYDIS_REGISTER_NONE,
 			.scale = 1,
 			.segment = ZYDIS_REGISTER_DS
 		};
 		X86Mem src_mem2 = {
 			.base = mem_reg2,
-			.disp = 0,
+			.disp = { 0 },
 			.index = ZYDIS_REGISTER_NONE,
 			.scale = 1,
 			.segment = ZYDIS_REGISTER_ES
@@ -880,7 +880,7 @@ IL_LIFTER(into) {
 
 #define JUMP_IL() \
 	do { \
-		RzILOpPure *jmp_addr = UN(analysis->bits, imm_value(ins->operands[0], pc, ins->ins_size)); \
+		RzILOpPure *jmp_addr = UN(analysis->bits, imm_value(ins->operands[0], pc)); \
 		if (ins->operands[0].size == 16 && analysis->bits != 64) { \
 			jmp_addr = LOGAND(jmp_addr, UN(analysis->bits, 0x0000ffff)); \
 		} \
@@ -1242,7 +1242,7 @@ IL_LIFTER(lodsq) {
 		} \
 \
 		RzILOpEffect *dec_counter = x86_il_set_reg(count_reg, SUB(x86_il_get_reg(count_reg), UN(addr_size, 1))); \
-		RzILOpEffect *true_cond = JMP(UN(analysis->bits, pc + imm_value(ins->operands[0], pc, ins->ins_size))); \
+		RzILOpEffect *true_cond = JMP(UN(analysis->bits, pc + imm_value(ins->operands[0], pc))); \
 		RzILOpEffect *branch = BRANCH(cond, true_cond, NOP()); \
 \
 		return SEQ2(dec_counter, branch); \
@@ -1328,14 +1328,14 @@ RzILOpEffect *x86_il_movs_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
 
 		X86Mem src_mem = {
 			.base = src_reg,
-			.disp = 0,
+			.disp = { 0 },
 			.index = ZYDIS_REGISTER_NONE,
 			.scale = 1,
 			.segment = ZYDIS_REGISTER_DS
 		};
 		X86Mem dst_mem = {
 			.base = dst_reg,
-			.disp = 0,
+			.disp = { 0 },
 			.index = ZYDIS_REGISTER_NONE,
 			.scale = 1,
 			.segment = ZYDIS_REGISTER_ES
@@ -1485,7 +1485,7 @@ IL_LIFTER(nop) {
  * One's complement negation
  * Encoding: M
  */
-IL_LIFTER(not) {
+IL_LIFTER(not ) {
 	return x86_il_set_op(0, LOGNOT(x86_il_get_op(0)));
 }
 
@@ -1501,7 +1501,7 @@ IL_LIFTER(not) {
 IL_LIFTER(or) {
 	RzILOpPure *op1 = x86_il_get_op(0);
 	RzILOpPure *op2 = x86_il_get_op(1);
-	RzILOpEffect *or = SETL("_or", LOGOR(op1, op2));
+	RzILOpEffect * or = SETL("_or", LOGOR(op1, op2));
 
 	RzILOpEffect *set_dest = x86_il_set_op(0, VARL("_or"));
 	RzILOpEffect *clear_of = SETG(EFLAGS(OF), IL_FALSE);
@@ -1596,7 +1596,7 @@ IL_LIFTER(popfq) {
 	return SEQ2(x86_il_set_flags(pop.val, 64), pop.eff);
 }
 
-#define CALCULATE_REX_PREFIX(rex) ((rex).W << 3 | (rex).R << 2 | (rex).X << 1 | (rex).B)
+#define CALCULATE_REX_PREFIX(rex) ((rex).W << 3 | (rex).R << 2 | (rex).X << 1 | (rex).B) /* in bytes */
 
 RzILOpEffect *x86_push_helper_impl(RzILOpPure *val, unsigned int user_op_size, unsigned int bitness, const X86ILIns *ins, ut64 pc) {
 	unsigned int dflag = user_op_size;
@@ -1606,7 +1606,7 @@ RzILOpEffect *x86_push_helper_impl(RzILOpPure *val, unsigned int user_op_size, u
 	if (ins) {
 		if (bitness == 64) {
 			dflag = CALCULATE_REX_PREFIX(ins->structure->raw.rex) ? 8 : ins->structure->raw.prefixes[2].value ? 2
-															  : 4; /* in bytes */
+															  : 4;
 			stack_size = 8; /* in bytes */
 		} else {
 			/* We use the other operand and address size if the prefix is set */
@@ -1723,23 +1723,23 @@ IL_LIFTER(pushaw) {
  * Push all general-purpose registers (32-bits)
  * Encoding: ZO
  */
-IL_LIFTER(pushal) {
-	if (analysis->bits != 32) {
-		return NULL;
-	}
-
-	RzILOpEffect *temp = SETL("_esp", x86_il_get_reg(ZYDIS_REGISTER_ESP));
-	RzILOpEffect *push = x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EAX), 4);
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_ECX), 4));
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EDX), 4));
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EBX), 4));
-	push = SEQ2(push, x86_push_helper(VARL("_esp"), 4));
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EBP), 4));
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_ESI), 4));
-	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EDI), 4));
-
-	return SEQ2(temp, push);
-}
+// IL_LIFTER(pushal) {
+//	if (analysis->bits != 32) {
+//		return NULL;
+//	}
+//
+//	RzILOpEffect *temp = SETL("_esp", x86_il_get_reg(ZYDIS_REGISTER_ESP));
+//	RzILOpEffect *push = x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EAX), 4);
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_ECX), 4));
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EDX), 4));
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EBX), 4));
+//	push = SEQ2(push, x86_push_helper(VARL("_esp"), 4));
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EBP), 4));
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_ESI), 4));
+//	push = SEQ2(push, x86_push_helper(x86_il_get_reg(ZYDIS_REGISTER_EDI), 4));
+//
+//	return SEQ2(temp, push);
+// }
 
 #define RCX_MACRO() \
 	ut8 size_in_bytes = ins->operands[0].size; \
@@ -1894,7 +1894,7 @@ IL_LIFTER(ret) {
 	if (ins->structure->operand_count_visible == 1) {
 		/* Immediate operand (Encoding: I)
 		 * Reduce RSP by that many bytes. */
-		ret = SEQ2(ret, x86_il_set_reg(ZYDIS_REGISTER_RSP, ADD(x86_il_get_reg(ZYDIS_REGISTER_RSP), UN(analysis->bits, imm_value(ins->operands[0], pc, ins->ins_size)))));
+		ret = SEQ2(ret, x86_il_set_reg(ZYDIS_REGISTER_RSP, ADD(x86_il_get_reg(ZYDIS_REGISTER_RSP), UN(analysis->bits, imm_value(ins->operands[0], pc)))));
 	}
 
 	return SEQ2(ret, JMP(VARL("tgt")));
@@ -1938,22 +1938,22 @@ IL_LIFTER(sahf) {
  * Encoding: M1, MC, MI
  * (Functionally the same as SHL)
  */
-IL_LIFTER(sal) {
-	SHIFT_MACRO();
-
-	RzILOpEffect *shifted = SETL("_shifted", SHIFTL0(UNSIGNED(size + 1, VARL("_pre_dest")), VARL("_shift")));
-
-	RzILOpEffect *result = SETL("_dest", UNSIGNED(size, VARL("_shifted")));
-
-	// if _shift == 0, CF is unaffected.
-	RzILOpEffect *set_cf = SETG(EFLAGS(CF), MSB(VARL("_shifted")));
-
-	// if _shift == 1, OF is set to 'CF xor MSB (after shift)'.
-	// otherwise, OF is undefined.
-	RzILOpEffect *set_of = SETG(EFLAGS(OF), XOR(VARG(EFLAGS(CF)), MSB(VARL("_dest"))));
-
-	return SEQ8(pre_dest, shift, shifted, result, set_cf, set_of, set_flags, set_dest);
-}
+// IL_LIFTER(sal) {
+//	SHIFT_MACRO();
+//
+//	RzILOpEffect *shifted = SETL("_shifted", SHIFTL0(UNSIGNED(size + 1, VARL("_pre_dest")), VARL("_shift")));
+//
+//	RzILOpEffect *result = SETL("_dest", UNSIGNED(size, VARL("_shifted")));
+//
+//	// if _shift == 0, CF is unaffected.
+//	RzILOpEffect *set_cf = SETG(EFLAGS(CF), MSB(VARL("_shifted")));
+//
+//	// if _shift == 1, OF is set to 'CF xor MSB (after shift)'.
+//	// otherwise, OF is undefined.
+//	RzILOpEffect *set_of = SETG(EFLAGS(OF), XOR(VARG(EFLAGS(CF)), MSB(VARL("_dest"))));
+//
+//	return SEQ8(pre_dest, shift, shifted, result, set_cf, set_of, set_flags, set_dest);
+// }
 
 /**
  * SAR
@@ -2324,46 +2324,46 @@ IL_LIFTER(test) {
  * Wait until not busy
  * ZO
  */
-IL_LIFTER(wait) {
-	/* NOP seems to be a reasonable implementation */
-	return NOP();
-}
+// IL_LIFTER(wait) {
+//	/* NOP seems to be a reasonable implementation */
+//	return NOP();
+// }
 
 /**
  * XCHG
  * Exchange data
  * Encoding: O, MR, RM
  */
-IL_LIFTER(xchg) {
-	RzILOpEffect *temp = SETL("_temp", x86_il_get_op(0));
-	RzILOpEffect *xchg = x86_il_set_op(0, x86_il_get_op(1));
-	RzILOpEffect *set_src = x86_il_set_op(1, VARL("_temp"));
-
-	return SEQ3(temp, xchg, set_src);
-}
+// IL_LIFTER(xchg) {
+//	RzILOpEffect *temp = SETL("_temp", x86_il_get_op(0));
+//	RzILOpEffect *xchg = x86_il_set_op(0, x86_il_get_op(1));
+//	RzILOpEffect *set_src = x86_il_set_op(1, VARL("_temp"));
+//
+//	return SEQ3(temp, xchg, set_src);
+// }
 
 /**
  * XLATB
  * Table look-up translation
  * Encoding: ZO
  */
-IL_LIFTER(xlatb) {
-	X86Mem mem;
-	mem.disp.value = 0;
-	mem.index = ZYDIS_REGISTER_NONE;
-	mem.scale = 1;
-	mem.segment = ZYDIS_REGISTER_DS;
-	mem.base = ZYDIS_REGISTER_EBX;
-
-	if (analysis->bits == 64) {
-		mem.segment = ZYDIS_REGISTER_NONE;
-		mem.base = ZYDIS_REGISTER_RBX;
-	} else if (analysis->bits == 16) {
-		mem.base = ZYDIS_REGISTER_BX;
-	}
-
-	return x86_il_set_reg(ZYDIS_REGISTER_AL, LOADW(8, ADD(x86_il_get_memaddr(mem), UNSIGNED(analysis->bits, x86_il_get_reg(ZYDIS_REGISTER_AL)))));
-}
+// IL_LIFTER(xlatb) {
+//	X86Mem mem;
+//	mem.disp.value = 0;
+//	mem.index = ZYDIS_REGISTER_NONE;
+//	mem.scale = 1;
+//	mem.segment = ZYDIS_REGISTER_DS;
+//	mem.base = ZYDIS_REGISTER_EBX;
+//
+//	if (analysis->bits == 64) {
+//		mem.segment = ZYDIS_REGISTER_NONE;
+//		mem.base = ZYDIS_REGISTER_RBX;
+//	} else if (analysis->bits == 16) {
+//		mem.base = ZYDIS_REGISTER_BX;
+//	}
+//
+//	return x86_il_set_reg(ZYDIS_REGISTER_AL, LOADW(8, ADD(x86_il_get_memaddr(mem), UNSIGNED(analysis->bits, x86_il_get_reg(ZYDIS_REGISTER_AL)))));
+// }
 
 /**
  * XOR
@@ -2373,7 +2373,7 @@ IL_LIFTER(xlatb) {
 IL_LIFTER(xor) {
 	RzILOpPure *op1 = x86_il_get_op(0);
 	RzILOpPure *op2 = x86_il_get_op(1);
-	RzILOpEffect *xor = SETL("_xor", LOGXOR(op1, op2));
+	RzILOpEffect * xor = SETL("_xor", LOGXOR(op1, op2));
 
 	RzILOpEffect *set_dest = x86_il_set_op(0, VARL("_xor"));
 	RzILOpEffect *clear_of = SETG(EFLAGS(OF), IL_FALSE);

librz/arch/isa/x86/x86_dwarf_regnum_table.h

@@ -2,6 +2,9 @@
 // SPDX-FileCopyrightText: 2024 Billow <[email protected]>
 // SPDX-License-Identifier: LGPL-3.0-only
 
+#ifndef X86_DWARF_REGNUM_TABLE_H
+#define X86_DWARF_REGNUM_TABLE_H
+
 #include <rz_types_base.h>
 
 /* x86_64 https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf */
@@ -84,3 +87,5 @@ static const char *map_dwarf_reg_to_x86_reg(ut32 reg_num) {
 		return "unsupported_reg";
 	}
 }
+
+#endif // X86_DWARF_REGNUM_TABLE_H

librz/arch/isa/x86/x86_il.h

@@ -7,7 +7,7 @@
 
 #include <rz_lib.h>
 #include <rz_analysis.h>
-#include <Zydis/Zydis.h>
+#include <Zydis.h>
 
 #define BITS_PER_BYTE    8
 #define GPR_FAMILY_COUNT 10
@@ -36,6 +36,6 @@ typedef struct x86_il_context_t {
 RZ_IPI bool rz_x86_il_opcode(RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RzAnalysisOp *aop, ut64 pc, RZ_BORROW RZ_NONNULL const X86ILIns *ins);
 RZ_IPI RzAnalysisILConfig *rz_x86_il_config(RZ_NONNULL RzAnalysis *analysis);
 
-#define imm_value(op, pc, ins_size) (ut64)((op.imm.is_relative) ? (op.imm.value.s + pc + ins_size) : (op.imm.value.u))
+#define imm_value(op, pc) (ut64)((op.imm.is_relative) ? (op.imm.value.s + pc) : (op.imm.value.u))
 
 #endif /* RZIL_ANALYSIS_X86_IL_H */