fixed #369 merge, updated rev date, rev history, changed spec to stable

Signed-off-by: Dan Smathers <[email protected]>

clic.adoc

@@ -38,9 +38,9 @@
 :stem: latexmath
 :description: RISC-V Core-Local Interrupt Controller
 :company: RISC-V.org
-:revdate: 02/09/2024
+:revdate: 03/04/2024
 :revnumber: 0.9-draft
-:revremark: This document is in the Development state. Assume anything can change. See https://wiki.riscv.org/display/HOME/Specification+States
+:revremark: This document is in the Stable state. Assume anything could still change, but limited change should be expected. See https://wiki.riscv.org/display/HOME/Specification+States
 :url-riscv: http://riscv.org
 :doctype: book
 //:doctype: report
@@ -133,6 +133,11 @@ Creative Commons Attribution 4.0 International License.
 [source]
 ----
 Date           	Description
+03/04/2024  issue #349 - Change access to CLIC registers from memory mapped to indirect CSR
+03/04/2024  pull #369  - Redefine parameters to no longer specify number of bit implemented but instead specify legal WARL values.
+03/04/2024  pull #373  - Add xcause.xpil fields to mandatory reset state.
+03/04/2024  issue #371 - Add additional clicinttrig enable for signaling interrupts claimed by xnxti.
+03/04/2024  issue #314 - xnxti now also returns SHV trap-handler entries
 02/09/2024  issue #360 - CLIC is allocated bit 53 in the stateen0 registers with the presumed bit name of CLIC.
 02/09/2024  issue #91  - Removed incorrect DTS entry. Moving DTS entry task to spike issue #242 instead of being in CLIC spec.
 02/05/2024  issue #367 - clicintip/ie clarification
@@ -712,7 +717,7 @@ If these registers are not implemented, they appear as hard-wired zeros.
 
 This logic is intended to be used with tmexttrigger.intctl as described in the RISC-V debug specification.
 
-Each interrupt trigger is a 32-bit memory-mapped WARL register with the
+Each interrupt trigger is a 32-bit WARL register with the
 following layout:
 
 [source]
@@ -1833,18 +1838,6 @@ these values configurable and initialized prior to CLIC operation.  The smclicco
 However, these parameters should functionally be considered static. If the value of these parameters are changed 
 during CLIC operation, CLIC behavior is undefined.  
 
-=== MCLICBASE
-The MCLICBASE parameter
-provides the base address of the m-mode CLIC memory mapped registers.
-Its value should be configured or set up at the platform level to indicate
-the starting address of m-mode CLIC memory mapped registers. 
-
-Since the CLIC memory map must be aligned at a 4KiB boundary, the MCLICBASE parameter
-has its 12 least-significant bits hardwired to zero. It is used
-to inform software about the location of CLIC m-mode memory mapped registers.
-
-Systems with CLIC memory mapped registers for additional privilege modes will provide additional xCLICBASE parameters for each of those CLIC x-mode memory mapped register regions.
-
 === NVBITS Parameter - Specifying Support for smclicshv Selective Interrupt Hardware Vectoring Extension
 
 The NVBITS Parameter specifies whether