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Resolve conflicts between PR #152 and branch master #211

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13edff8
Add L1 Instruction Cache
Feb 8, 2024
431e74e
Connect up ICache to Fetch
Feb 11, 2024
b09fd6c
Fix rename and issue tests accounting for icache latency
Feb 12, 2024
4dee506
Fix LSU test accounting for extra ICache latency
Feb 12, 2024
9c77264
Fix L2Cache tests. Change L2+MSS to use credit instead of ack
Feb 12, 2024
7fd5471
Add fetch block size, and buffer size parameters to Fetch
Feb 16, 2024
58a9f4c
Merge branch 'master' into danbone/issue_143_icache
danbone Feb 16, 2024
063a6f3
Merge remote-tracking branch 'upstream/master' into danbone/issue_143…
Feb 20, 2024
50acbb1
update dcache comments on L2Cache credits
Feb 26, 2024
b020c81
Merge branch 'danbone/issue_143_icache' of https://github.com/danbone…
Feb 26, 2024
9b46b07
Resolve conflicts between branch 'master' and 'danbone/issue_143_icac…
dragon540 Sep 26, 2024
b5955c9
Merge branch 'shobhit/issue_143_icache' of github.com:dragon540/riscv…
dragon540 Sep 26, 2024
7e225d1
Removed extra files
dragon540 Oct 1, 2024
abd5f23
Fusing instructions only when enough instructions are sent from fetch
dragon540 Oct 15, 2024
1a56ca9
Replaced condition using hardcoded value with condition using attribu…
dragon540 Oct 18, 2024
caddbf3
Merge branch 'master' into shobhit/issue_143_icache
dragon540 Oct 19, 2024
515e160
updated EXPECTED files and ../core/Inst.hpp for whitespace between pi…
dragon540 Oct 19, 2024
e73e93a
Remove generated log files
dragon540 Oct 21, 2024
f0b0f05
Revert stflib to be consistent with upstream branch
dragon540 Oct 31, 2024
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8 changes: 8 additions & 0 deletions .idea/.gitignore

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32 changes: 32 additions & 0 deletions .idea/codeStyles/Project.xml

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5 changes: 5 additions & 0 deletions .idea/codeStyles/codeStyleConfig.xml

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15 changes: 15 additions & 0 deletions .idea/editor.xml

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11 changes: 11 additions & 0 deletions .idea/misc.xml

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8 changes: 8 additions & 0 deletions .idea/modules.xml

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2 changes: 2 additions & 0 deletions .idea/riscv-perf-model.iml

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10 changes: 10 additions & 0 deletions .idea/vcs.xml

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2 changes: 1 addition & 1 deletion arches/fusion.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ top.cpu.core0:
decode:
params:
num_to_decode: 8
fusion_enable: true
fusion_enable: false
fusion_debug: false
fusion_enable_register: 0xFFFFFFFF
fusion_max_latency: 8
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