Add decoupled branch predictor

core/CMakeLists.txt

@@ -1,6 +1,7 @@
 project (core)
 add_library(core
   Core.cpp
+  ICache.cpp
   Fetch.cpp
   Decode.cpp
   Rename.cpp

core/CPUFactories.hpp

@@ -5,6 +5,7 @@
 
 #include "sparta/simulation/ResourceFactory.hpp"
 #include "Core.hpp"
+#include "ICache.hpp"
 #include "Fetch.hpp"
 #include "Decode.hpp"
 #include "Rename.hpp"
@@ -39,6 +40,10 @@ namespace olympia{
         sparta::ResourceFactory<olympia::Core,
                                 olympia::Core::CoreParameterSet> core_rf;
 
+        //! \brief Resource Factory to build an Instruction Cache Unit
+        sparta::ResourceFactory<olympia::ICache,
+                olympia::ICache::ICacheParameterSet> icache_rf;
+
         //! \brief Resource Factory to build a Fetch Unit
         sparta::ResourceFactory<olympia::Fetch,
                                 olympia::Fetch::FetchParameterSet> fetch_rf;
@@ -56,8 +61,7 @@ namespace olympia{
         //! \brief Resource Factory to build a Execute Unit
         ExecuteFactory  execute_rf;
 
-
-        //! \brief Resource Factory to build a MMU Unit
+        //! \brief Resource Factory to build a Data Cache Unit
         sparta::ResourceFactory<olympia::DCache,
                 olympia::DCache::CacheParameterSet> dcache_rf;
 
@@ -100,7 +104,7 @@ namespace olympia{
         // //! \brief Resource Factory to build a IssueQueue Unit
         // sparta::ResourceFactory<olympia::IssueQueue,
         //                         olympia::IssueQueue::IssueQueueParameterSet> issue_queue_rf;
-                            
+
         //! \brief Set up the Mavis Decode functional unit
         MavisFactory  mavis_rf;
     }; // struct CPUFactories

core/CPUTopology.cpp

@@ -27,6 +27,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
             sparta::TreeNode::GROUP_IDX_NONE,
             &factories->flushmanager_rf
         },
+        {
+            "icache",
+            "cpu.core*",
+            "Instruction Cache Unit",
+            sparta::TreeNode::GROUP_NAME_NONE,
+            sparta::TreeNode::GROUP_IDX_NONE,
+            &factories->icache_rf
+        },
         {
             "fetch",
             "cpu.core*",
@@ -152,6 +160,18 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
 
     //! Instantiating ports of this topology
     port_connections = {
+        {
+            "cpu.core*.fetch.ports.out_fetch_icache_req",
+            "cpu.core*.icache.ports.in_fetch_req"
+        },
+        {
+            "cpu.core*.fetch.ports.in_icache_fetch_resp",
+            "cpu.core*.icache.ports.out_fetch_resp"
+        },
+        {
+            "cpu.core*.fetch.ports.in_icache_fetch_credits",
+            "cpu.core*.icache.ports.out_fetch_credit"
+        },
         {
             "cpu.core*.fetch.ports.out_fetch_queue_write",
             "cpu.core*.decode.ports.in_fetch_queue_write"
@@ -213,20 +233,32 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
             "cpu.core*.l2cache.ports.in_dcache_l2cache_req"
         },
         {
-            "cpu.core*.dcache.ports.in_l2cache_ack",
-            "cpu.core*.l2cache.ports.out_l2cache_dcache_ack"
+            "cpu.core*.dcache.ports.in_l2cache_credits",
+            "cpu.core*.l2cache.ports.out_l2cache_dcache_credits"
         },
         {
             "cpu.core*.dcache.ports.in_l2cache_resp",
             "cpu.core*.l2cache.ports.out_l2cache_dcache_resp"
         },
+        {
+            "cpu.core*.icache.ports.out_l2cache_req",
+            "cpu.core*.l2cache.ports.in_icache_l2cache_req"
+        },
+        {
+            "cpu.core*.icache.ports.in_l2cache_credits",
+            "cpu.core*.l2cache.ports.out_l2cache_icache_credits"
+        },
+        {
+            "cpu.core*.icache.ports.in_l2cache_resp",
+            "cpu.core*.l2cache.ports.out_l2cache_icache_resp"
+        },
         {
             "cpu.core*.l2cache.ports.out_l2cache_biu_req",
             "cpu.core*.biu.ports.in_biu_req"
         },
         {
-            "cpu.core*.biu.ports.out_biu_ack",
-            "cpu.core*.l2cache.ports.in_biu_l2cache_ack"
+            "cpu.core*.biu.ports.out_biu_credits",
+            "cpu.core*.l2cache.ports.in_biu_l2cache_credits"
         },
         {
             "cpu.core*.biu.ports.out_biu_resp",

core/DCache.cpp

@@ -11,8 +11,8 @@ namespace olympia {
         in_lsu_lookup_req_.registerConsumerHandler
             (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getInstsFromLSU_, MemoryAccessInfoPtr));
 
-        in_l2cache_ack_.registerConsumerHandler
-            (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, uint32_t));
+        in_l2cache_credits_.registerConsumerHandler
+            (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t));
 
         in_l2cache_resp_.registerConsumerHandler
             (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr));
@@ -99,13 +99,13 @@ namespace olympia {
         busy_ = false;
     }
 
-    void DCache::getAckFromL2Cache_(const uint32_t &ack) {
+    void DCache::getCreditsFromL2Cache_(const uint32_t &ack) {
         // When DCache sends the request to L2Cache for a miss,
         // This bool will be set to false, and Dcache should wait for ack from
         // L2Cache notifying DCache that there is space in it's dcache request buffer
         //
         // Set it to true so that the following misses from DCache can be sent out to L2Cache.
-        dcache_l2cache_credits_ = ack;
+        dcache_l2cache_credits_ += ack;
     }
 
 }

core/DCache.hpp

@@ -38,7 +38,7 @@ namespace olympia
 
         void getInstsFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr);
 
-        void getAckFromL2Cache_(const uint32_t & ack);
+        void getCreditsFromL2Cache_(const uint32_t &);
 
         void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);
 
@@ -59,7 +59,7 @@ namespace olympia
         sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_{&unit_port_set_,
                                                                    "in_lsu_lookup_req", 0};
 
-        sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};
+        sparta::DataInPort<uint32_t> in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1};
 
         sparta::DataInPort<MemoryAccessInfoPtr> in_l2cache_resp_{&unit_port_set_,
                                                                  "in_l2cache_resp", 1};