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Add L1 Instruction Cache#152

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danbone wants to merge 10 commits intoriscv-software-src:masterriscv-software-src/riscv-perf-model:masterfrom danbone:danbone/issue_143_icachedanbone/riscv-perf-model:danbone/issue_143_icacheCopy head branch name to clipboard

+1,548-242

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Commits on Feb 8, 2024

• Add L1 Instruction Cache

  

  Daniel Bone

  committed
  13edff8

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Commits on Feb 11, 2024

• Connect up ICache to Fetch

  

  Daniel Bone

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  431e74e

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Commits on Feb 12, 2024

• Fix rename and issue tests accounting for icache latency

  

  Daniel Bone

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  b09fd6c

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• Fix LSU test accounting for extra ICache latency

  

  Daniel Bone

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  4dee506

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• Fix L2Cache tests. Change L2+MSS to use credit instead of ack

  

  Daniel Bone

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  9c77264

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Commits on Feb 16, 2024

• Add fetch block size, and buffer size parameters to Fetch

  

  Daniel Bone

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  7fd5471

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• Merge branch 'master' into danbone/issue_143_icache

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  danbone

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Commits on Feb 20, 2024

• Merge remote-tracking branch 'upstream/master' into danbone/issue_143_icache

  

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Commits on Feb 26, 2024

• update dcache comments on L2Cache credits

  

  Daniel Bone

  committed
  50acbb1

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• Merge branch 'danbone/issue_143_icache' of https://github.com/danbone/riscv-perf-model into danbone/issue_143_icache

  

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