Merge branch 'master' into vfloat_sequencing

Signed-off-by: Isaac David <[email protected]>

.github/workflows/macos-build.yml

@@ -12,7 +12,7 @@ jobs:
     strategy:
       # Strategy is a matrix of debug and release builds/regression
       matrix:
-        os: [macos-12]
+        os: [macos-14]
         BUILD_TYPE: [Debug]
         COMPILER: [clang]
 

arches/isa_json/gen_uarch_rv64v_json.py

@@ -243,7 +243,7 @@
     "vnclip.wx" : {"pipe" : "vfixed", "uop_gen" : "NARROWING", "latency" : 2},
     "vnclip.wi" : {"pipe" : "vfixed", "uop_gen" : "NARROWING", "latency" : 2},
 
-    # Vector Floating-Point Instructions: Vector Single-Width Floating-Point Add/Subtract Instructions
+# Vector Floating-Point Instructions: Vector Single-Width Floating-Point Add/Subtract Instructions
     "vfadd.vv" :  {"pipe" : "vfloat", "uop_gen" : "ELEMENTWISE", "latency" : 6},
     "vfadd.vf" :  {"pipe" : "vfloat", "uop_gen" : "ELEMENTWISE", "latency" : 6},
 

core/Decode.cpp

@@ -5,6 +5,7 @@
 #include "fsl_api/FusionTypes.h"
 
 #include "sparta/events/StartupEvent.hpp"
+#include "sparta/statistics/Counter.hpp"
 #include "sparta/utils/LogUtils.hpp"
 #include <algorithm>
 #include <iostream>
@@ -48,7 +49,13 @@ namespace olympia
         fusion_summary_report_(p->fusion_summary_report),
         fusion_group_definitions_(p->fusion_group_definitions),
         vector_enabled_(true),
-        vector_config_(new VectorConfig(p->init_vl, p->init_sew, p->init_lmul, p->init_vta))
+        vector_config_(new VectorConfig(p->init_vl, p->init_sew, p->init_lmul, p->init_vta)),
+        vset_blocking_count_(&unit_stat_set_, "vset_blocking_count",
+                             "Number of times that the Decode unit blocks execution",
+                             sparta::Counter::COUNT_NORMAL),
+        vset_blocking_stall_latency_(&unit_stat_set_, "vset_blocking_stall_latency",
+                                     "Accumulated between roundtrip vset decode and processing",
+                                     sparta::Counter::COUNT_NORMAL)
     {
         initializeFusion_();
 
@@ -77,9 +84,9 @@ namespace olympia
         fetch_queue_credits_outp_.send(fetch_queue_.capacity());
 
         // Get pointer to the vector uop generator
-        sparta::TreeNode * root_node = getContainer()->getRoot();
-        vec_uop_gen_ = \
-            root_node->getChild("cpu.core0.decode.vec_uop_gen")->getResourceAs<olympia::VectorUopGenerator*>();
+        sparta::TreeNode* root_node = getContainer()->getRoot();
+        vec_uop_gen_ = root_node->getChild("cpu.core0.decode.vec_uop_gen")
+                           ->getResourceAs<olympia::VectorUopGenerator*>();
     }
 
     // -------------------------------------------------------------------
@@ -135,9 +142,9 @@ namespace olympia
         const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID();
         if ((uid == MAVIS_UID_VSETVLI) && inst->hasZeroRegSource())
         {
-            const uint32_t new_vl = \
-                inst->hasZeroRegDest() ? std::min(vector_config_->getVL(), vector_config_->getVLMAX())
-                                       : vector_config_->getVLMAX();
+            const uint32_t new_vl = inst->hasZeroRegDest() ? std::min(vector_config_->getVL(),
+                                                                      vector_config_->getVLMAX())
+                                                           : vector_config_->getVLMAX();
             vector_config_->setVL(new_vl);
         }
 
@@ -153,6 +160,8 @@ namespace olympia
         // if rs1 != 0, VL = x[rs1], so we assume there's an STF field for VL
         if (waiting_on_vset_)
         {
+            const auto vset_block_end = getClock()->currentCycle();
+            vset_blocking_stall_latency_ += (vset_block_end - vset_block_start_);
             // schedule decode, because we've been stalled on vset
             waiting_on_vset_ = false;
             ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0));
@@ -192,8 +201,7 @@ namespace olympia
         InstUidListType uids;
 
         // Send instructions on their way to rename
-        InstGroupPtr insts =
-            sparta::allocate_sparta_shared_pointer<InstGroup>(instgroup_allocator);
+        InstGroupPtr insts = sparta::allocate_sparta_shared_pointer<InstGroup>(instgroup_allocator);
         // if we have a waiting on vset followed by more instructions, we decode
         // vset and stall anything else
         while ((insts->size() < num_to_decode) && !waiting_on_vset_)
@@ -207,7 +215,7 @@ namespace olympia
             else if (fetch_queue_.size() > 0)
             {
                 sparta_assert(fetch_queue_.size() > 0,
-                     "Cannot read from the fetch queue because it is empty!");
+                              "Cannot read from the fetch queue because it is empty!");
                 auto & inst = fetch_queue_.read(0);
 
                 // for vector instructions, we block on vset and do not allow any other
@@ -219,13 +227,16 @@ namespace olympia
                 // vsetvli only blocks if rs1 is not x0
                 // vsetivli never blocks
                 const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID();
-                if ((uid == MAVIS_UID_VSETIVLI) ||
-                   ((uid == MAVIS_UID_VSETVLI) && inst->hasZeroRegSource()))
+                if ((uid == MAVIS_UID_VSETIVLI)
+                    || ((uid == MAVIS_UID_VSETVLI) && inst->hasZeroRegSource()))
                 {
                     updateVectorConfig_(inst);
                 }
                 else if (uid == MAVIS_UID_VSETVLI || uid == MAVIS_UID_VSETVL)
                 {
+                    ++vset_blocking_count_;
+
+                    vset_block_start_ = getClock()->currentCycle();
                     // block for vsetvl or vsetvli when rs1 of vsetvli is NOT 0
                     waiting_on_vset_ = true;
                     // need to indicate we want a signal sent back at execute
@@ -246,7 +257,8 @@ namespace olympia
                 // Even if LMUL == 1, we need the vector uop generator to create a uop for us
                 // because some generators will add additional sources and destinations to the
                 // instruction (e.g. widening, multiply-add, slides).
-                if (inst->isVector() && !inst->isVset() && (inst->getUopGenType() != InstArchInfo::UopGenType::NONE))
+                if (inst->isVector() && !inst->isVset()
+                    && (inst->getUopGenType() != InstArchInfo::UopGenType::NONE))
                 {
                     ILOG("Vector uop gen: " << inst);
                     vec_uop_gen_->setInst(inst);

core/Decode.hpp

@@ -341,6 +341,11 @@ namespace olympia
 
         uint32_t getNumVecUopsRemaining() const;
 
+        sparta::Counter vset_blocking_count_;
+        sparta::Counter vset_blocking_stall_latency_;
+
+        uint64_t vset_block_start_;
+
         //////////////////////////////////////////////////////////////////////
         // Decoder callbacks
         void sendInitialCredits_();

core/Dispatch.hpp

@@ -238,6 +238,7 @@ namespace olympia
                 sparta::Counter(getStatisticSet(), "count_vfmul_insts", "Total VFMUL insts",
                                 sparta::Counter::COUNT_NORMAL),
                 sparta::Counter(getStatisticSet(), "count_vfdiv_insts", "Total VFDIV insts",
+
                                 sparta::Counter::COUNT_NORMAL),
                 sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts",
                                 sparta::Counter::COUNT_NORMAL),

docs/design_document_template/README.md

@@ -0,0 +1,14 @@
+# Design document template for Olympia development
+
+This provides a starting point or template for design document development.
+
+This is adoc format which has use else where in RVI documentation.
+
+There is a convention for images, using the ./media directory
+
+There are a number of free editors available for adoc: clion, VS code, etc.
+
+## Contents
+
+olympiaDesignDocUnitTemplate.adoc
+./media/image1.png

docs/design_document_template/olympiaDesignDocUnitTemplate.adoc

@@ -0,0 +1,159 @@
+:doctitle: Olympia Design Document Template
+
+:toc:
+
+[[Document_Information]]
+== Document Information
+
+<meta data>
+
+[[Revision_History]]
+=== Revision History
+
+<newest revision at the top of this table>
+
+[width="100%",cols="11%,11%,16%,62%",options="header",]
+|===
+|*Revision* |*Date*      |*Author*  |*Summary of Changes*
+|0.?        | 2024.11.12 | <author> | <next change>
+|0.1        | 2024.11.12 | Jeff Nye | initial template
+|===
+
+[[Conventions_and_Terminology]]
+=== Conventions and Terminology
+
+<terms or acronyms used in the document that may not have general visibility>
+
+[width="100%",cols="17%,83%",options="header",]
+|===
+|Label |Description
+|<label> |<description
+| |
+|===
+
+[[Related_Documents]]
+=== Related Documents
+
+<external documents relevant to the unit>
+[width="100%",cols="25%,75%",options="header",]
+|===
+|*Title* |*Description*
+| The RISC-V Instruction Set Manual Volume I | https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view?usp=drive_link[Unprivileged Architecture Version 2024041]
+| | |
+| | |
+|===
+
+
+[[Notes_Open_Issues]]
+=== Notes/Open Issues
+
+<advisories, limitations, unsolved problems>
+
+* Note1
+* Note 2
+
+[[OVERVIEW]]
+== OVERVIEW
+
+<Overview of the unit, what does it do, where does it fit into Olympia
+proper, use the section below to discuss the context>
+
+[[Overview_Block_Diagram]]
+=== Overview Block Diagram
+
+<Add an overview block diagram>
+
+[[Functional_Description]]
+== Functional Description
+
+<this begins the detailed description of the unit. Typically, this
+discusses each major block in a separate sub-section>
+
+[[Unit_Block_Diagram]]
+=== Unit Block Diagram
+
+<Add an overview block diagram>
+
+image:media/image1.png[image,width=576,height=366]
+
+Figure 1 - Sample Figure
+
+
+[[Block_Diagram_Description]]
+=== Block Diagram Description
+
+<walk through the block diagram>
+
+[[Description_of_Block_B1]]
+== Description of Block <B1>
+
+<this section contains block level details>
+
+[[Operation]]
+=== Operation
+
+<describe the low-level operation of the block>
+
+[[Interfaces]]
+=== Interfaces
+
+<this is typically a general list of block interfaces, this changes with
+development, final design will finalize this section>
+
+[width="100%",cols="18%,21%,61%",options="header",]
+|===
+|*Name* |*C++ Type* |*Purpose/Description*
+| | |
+| | |
+| | |
+|===
+
+[[CPP_Class_Description]]
+=== C++ Class Description
+
+<describe the class, it’s inheritance assumptions and data structures
+used by the class
+
+[[Parameterization]]
+=== Parameterization
+
+<top level parameterization, include hidden and those visible in arch
+yaml>
+
+[[Test_Bench_Description]]
+== Test Bench Description
+
+<description of what is covered by the test bench, description of each
+test as appropriate
+
+[[Description_of_Test_1]]
+=== Description of Test 1
+
+<discuss test 1>
+
+[[Description_of_Test_2]]
+=== Description of Test 2
+
+<discuss test 2>
+
+[[Future_Work_or_Features]]
+== Future Work or Features
+
+<forward looking statements>
+
+[[References_Citations]]
+== References/Citations
+
+<Add references as needed>
+
+[1] <insert citation>
+
+[[Appendices]]
+== Appendices
+
+<as needed>
+
+[[Appendix_1]]
+=== Appendix 1
+
+<as needed>

test/core/vector/traces/add_vl256_e32_m1_ta.json

@@ -0,0 +1,43 @@
+[
+  {
+    "mnemonic": "vsetvli",
+    "vtype": "0x2",
+    "rd": 0,
+    "rs1": 13,
+    "vl": 256,
+    "vta": 1
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 0,
+    "rs1": 10,
+    "vaddr": "0xdaedbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 1,
+    "rs1": 11,
+    "vaddr": "0xdaadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vadd.v",
+    "vd": 2,
+    "vs2": 0,
+    "vs1": 1
+  },
+  {
+    "mnemonic": "vse32.v",
+    "vs3": 2,
+    "rs1": 12,
+    "vaddr": "0xdeadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  }
+]