Initialize link register with a code address in TEST_JAL_OP.

[cr1901]

Description

This PR initializes the link register in TEST_JAL_OP to a code address. Without this line, RV32I_Zicsr-only cores that don't understand compressed instructions fail to match SAIL in the misalign-jal-01.S test by a single bit. Initializing the link register makes such cores match SAIL (absent other bugs in such cores :)...).

Related Issues

#445

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

RV32I_Zicsr, without C extension.

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
  The provided command in the docs doesn't appear to work; I don't know where to get CGFs. Also, this is a bug fix, not a new test.
• Link to Google-Drive folder containing the new coverage reports (See this for more info): Not applicable? See above.

Optional Checklist:

• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[allenjbaum]

This fixes a bug where test computes a delta of two addresses, one of which is supposed to be the link register, but because the JAL traps, no link is written.
models with different load addresses will fail to match. This fixes initializes the link to a valid address,