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debug stub fixes, MMU log tweak #90

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merged 5 commits into from
Jul 8, 2024
Merged

debug stub fixes, MMU log tweak #90

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3ebda0b
Hexagon: lldb read/write predicate registers p0/p1/p2/p3
taylorsimpson Jun 12, 2024
2cc2b3b
Fix typo in hexagon-sys.xml
taylorsimpson Jun 12, 2024
e0937b9
Hexagon (target/hexagon) print new mode on mode change
taylorsimpson Jun 12, 2024
870e8d6
Hexagon (target/hexagon) optimize gen_read_greg
taylorsimpson Jun 12, 2024
c22e902
Fix system/guest registers in hexagon-sys.xml
taylorsimpson Jun 25, 2024
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6 changes: 5 additions & 1 deletion gdb-xml/hexagon-core.xml
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
<?xml version="1.0"?>
<!--
Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
Copyright(c) 2023-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.

This work is licensed under the terms of the GNU GPL, version 2 or
(at your option) any later version. See the COPYING file in the
Expand Down Expand Up @@ -80,5 +80,9 @@
<reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/>
<reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/>
<reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/>
<reg name="p0" bitsize="8" offset="256" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="64"/>
<reg name="p1" bitsize="8" offset="257" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="65"/>
<reg name="p2" bitsize="8" offset="258" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="66"/>
<reg name="p3" bitsize="8" offset="259" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="67"/>

</feature>
33 changes: 28 additions & 5 deletions gdb-xml/hexagon-sys.xml
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Expand Up @@ -80,10 +80,33 @@
<reg name="rsv61" bitsize="32" offset="4660" encoding="uint" format="hex" group="System Registers" dwarf_regnum="196" />
<reg name="rsv62" bitsize="32" offset="4664" encoding="uint" format="hex" group="System Registers" dwarf_regnum="197" />
<reg name="rsv63" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="g0" bitsize="32" offset="4672" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="179" />
<reg name="g1" bitsize="32" offset="4676" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="180" />
<reg name="g2" bitsize="32" offset="4680" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="181" />
<reg name="g3" bitsize="32" offset="4684" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="182" />
<reg name="commit1t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit2t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit3t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit4t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit5t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit6t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle1t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle2t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle3t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle4t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle5t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle6t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="stfinst" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="isdbcmd" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="isdbver" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="brkptinfo" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="rgdr3" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit7t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="commit8t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle7t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="pcycle8t" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />
<reg name="rsv85" bitsize="32" offset="4668" encoding="uint" format="hex" group="System Registers" dwarf_regnum="198" />

<reg name="gelr" altname="g0" bitsize="32" offset="4672" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="179" />
<reg name="gsr" altname="g1" bitsize="32" offset="4676" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="180" />
<reg name="gosp" altname="g2" bitsize="32" offset="4680" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="181" />
<reg name="gbadva" altname="g3" bitsize="32" offset="4684" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="182" />
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<reg name="rsv4" bitsize="32" offset="4688" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="183" />
<reg name="rsv5" bitsize="32" offset="4692" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="184" />
<reg name="rsv6" bitsize="32" offset="4696" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="185" />
Expand All @@ -95,7 +118,7 @@
<reg name="rsv12" bitsize="32" offset="4720" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="191" />
<reg name="rsv13" bitsize="32" offset="4724" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="192" />
<reg name="rsv14" bitsize="32" offset="4728" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="193" />
<reg name="rsv15," bitsize="32" offset="4732" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="194" />
<reg name="rsv15" bitsize="32" offset="4732" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="194" />
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<reg name="gpmucnt4" bitsize="32" offset="4736" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="195" />
<reg name="gpmucnt5" bitsize="32" offset="4740" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="196" />
<reg name="gpmucnt6" bitsize="32" offset="4744" encoding="uint" format="hex" group="Guest Registers" dwarf_regnum="197" />
Expand Down
2 changes: 1 addition & 1 deletion target/hexagon/cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1136,7 +1136,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
cc->get_pc = hexagon_cpu_get_pc;
cc->gdb_read_register = hexagon_gdb_read_register;
cc->gdb_write_register = hexagon_gdb_write_register;
cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;
cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_PREGS;
cc->gdb_stop_before_watchpoint = true;
cc->gdb_core_xml_file = "hexagon-core.xml";
cc->disas_set_info = hexagon_cpu_disas_set_info;
Expand Down
15 changes: 14 additions & 1 deletion target/hexagon/gdbstub.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -39,6 +39,12 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)

n -= TOTAL_PER_THREAD_REGS;

if (n < NUM_PREGS) {
return gdb_get_reg8(mem_buf, env->pred[n]);
}

n -= NUM_PREGS;
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g_assert_not_reached();
return 0;
}
Expand All @@ -62,6 +68,13 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
n -= TOTAL_PER_THREAD_REGS;

if (n < NUM_PREGS) {
env->pred[n] = ldtul_p(mem_buf) & 0xff;
return sizeof(uint8_t);
}

n -= NUM_PREGS;

g_assert_not_reached();
return 0;
}
Expand Down
12 changes: 10 additions & 2 deletions target/hexagon/genptr.c
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Expand Up @@ -344,12 +344,20 @@ static void gen_read_sreg_pair(TCGv_i64 dst, int reg_num)

static void gen_read_greg(TCGv dst, int reg_num)
{
gen_helper_greg_read(dst, tcg_env, tcg_constant_tl(reg_num));
if (reg_num <= HEX_GREG_G3) {
tcg_gen_mov_tl(dst, hex_greg[reg_num]);
} else {
gen_helper_greg_read(dst, tcg_env, tcg_constant_tl(reg_num));
}
}

static void gen_read_greg_pair(TCGv_i64 dst, int reg_num)
{
gen_helper_greg_read_pair(dst, tcg_env, tcg_constant_tl(reg_num));
if (reg_num == HEX_GREG_G0 || reg_num == HEX_GREG_G2) {
tcg_gen_concat_i32_i64(dst, hex_greg[reg_num], hex_greg[reg_num + 1]);
} else {
gen_helper_greg_read_pair(dst, tcg_env, tcg_constant_tl(reg_num));
}
}
#endif

Expand Down
3 changes: 2 additions & 1 deletion target/hexagon/hex_mmu.c
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Expand Up @@ -280,7 +280,8 @@ void hex_mmu_off(CPUHexagonState *env)

void hex_mmu_mode_change(CPUHexagonState *env)
{
qemu_log_mask(CPU_LOG_MMU, "Hexagon mode change!\n");
qemu_log_mask(CPU_LOG_MMU, "Hexagon mode change: new mode is %s\n",
get_sys_str(env));
CPUState *cs = env_cpu(env);
tlb_flush(cs);
}
Expand Down
8 changes: 4 additions & 4 deletions target/hexagon/op_helper.c
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Expand Up @@ -2412,16 +2412,16 @@ void HELPER(sreg_write_pair)(CPUHexagonState *env, uint32_t reg, uint64_t val)
uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg)

{
/* Check should be done before calling this helper */
g_assert(reg > HEX_GREG_G3);
return hexagon_greg_read(env, reg);
}

uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)

{
if (reg == HEX_GREG_G0 || reg == HEX_GREG_G2) {
return (uint64_t)(env->greg[reg]) |
(((uint64_t)(env->greg[reg + 1])) << 32);
}
/* Check should be done before calling this helper */
g_assert(reg > HEX_GREG_G3);
switch (reg) {
case HEX_GREG_GPCYCLELO: {
target_ulong ssr = ARCH_GET_SYSTEM_REG(env, HEX_SREG_SSR);
Expand Down