Merge branch 'nav/mx/flamingo' into nav/mx_icache/flamingo

Bender.yml

@@ -148,7 +148,6 @@ sources:
     - hw/ip/spatz/src/rvv_pkg.sv
     # Level 1
     - hw/ip/spatz/src/generated/spatz_pkg.sv
-
     - hw/ip/spatz/src/spatz_serdiv.sv
     # Level 2
     - hw/ip/spatz/src/spatz_decoder.sv
@@ -161,6 +160,7 @@ sources:
     - hw/ip/spatz/src/spatz_vlsu.sv
     - hw/ip/spatz/src/spatz_vrf.sv
     - hw/ip/spatz/src/spatz_vsldu.sv
+    - hw/ip/spatz/src/spatz_mxu.sv
     # Level 4
     - hw/ip/spatz/src/spatz_controller.sv
     # Level 5

Makefile

@@ -11,7 +11,7 @@ include util/Makefrag
 BENDER_VERSION = 0.27.1
 
 # Do not include minifloat opcodes, since they conflict with the RVV opcodes!
-OPCODES := "opcodes-rvv opcodes-rv32b_CUSTOM opcodes-ipu_CUSTOM opcodes-frep_CUSTOM opcodes-dma_CUSTOM opcodes-ssr_CUSTOM opcodes-smallfloat"
+OPCODES := "opcodes-rvv opcodes-rv32b_CUSTOM opcodes-ipu_CUSTOM opcodes-frep_CUSTOM opcodes-dma_CUSTOM opcodes-ssr_CUSTOM opcodes-smallfloat opcodes-rmm"
 
 # Default target
 all: bender toolchain update_opcodes
@@ -34,14 +34,14 @@ sw/toolchain/riscv-gnu-toolchain: sw/toolchain/riscv-gnu-toolchain.version
 
 sw/toolchain/llvm-project: sw/toolchain/llvm-project.version
 	mkdir -p sw/toolchain
-	cd sw/toolchain && git clone git@github.com:pulp-platform/llvm-project.git
+	cd sw/toolchain && git clone https://github.com/mp-17/llvm-project.git
 	cd sw/toolchain/llvm-project &&                  \
 		git checkout `cat ../llvm-project.version` && \
 		git submodule update --init --recursive --jobs=8 .
 
 sw/toolchain/riscv-opcodes: sw/toolchain/riscv-opcodes.version
 	mkdir -p sw/toolchain
-	cd sw/toolchain && git clone https://github.com/pulp-platform/riscv-opcodes.git
+	cd sw/toolchain && git clone https://github.com/mp-17/riscv-opcodes.git
 	cd sw/toolchain/riscv-opcodes &&                 \
 		git checkout `cat ../riscv-opcodes.version` && \
 		git submodule update --init --recursive --jobs=8 .

hw/ip/snitch/src/snitch.sv

@@ -2263,6 +2263,9 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
         end
       end
       // 1 source register (rs1) and 1 destination register (rd)
+      riscv_instr::MSETTILEM,
+      riscv_instr::MSETTILEK,
+      riscv_instr::MSETTILEN,
       riscv_instr::VSETVLI: begin
         if (RVV) begin
           write_rd        = 1'b0;
@@ -2353,6 +2356,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VMULHU_VV,
       riscv_instr::VMULHSU_VV,
       riscv_instr::VMACC_VV,
+      riscv_instr::MXMACC_VV,
       riscv_instr::VNMSAC_VV,
       riscv_instr::VMADD_VV,
       riscv_instr::VNMSUB_VV,
@@ -2389,6 +2393,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VFSGNJX_VV,
       riscv_instr::VFMUL_VV,
       riscv_instr::VFMADD_VV,
+      riscv_instr::MXFMACC_VV,
       riscv_instr::VFNMADD_VV,
       riscv_instr::VFMSUB_VV,
       riscv_instr::VFNMSUB_VV,
@@ -2465,6 +2470,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VMULHU_VX,
       riscv_instr::VMULHSU_VX,
       riscv_instr::VMACC_VX,
+      riscv_instr::MXMACC_VX,
       riscv_instr::VNMSAC_VX,
       riscv_instr::VMADD_VX,
       riscv_instr::VNMSUB_VX,
@@ -2513,6 +2519,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VFMSUB_VF,
       riscv_instr::VFNMSUB_VF,
       riscv_instr::VFMACC_VF,
+      riscv_instr::MXFMACC_VF,
       riscv_instr::VFNMACC_VF,
       riscv_instr::VFMSAC_VF,
       riscv_instr::VFNMSAC_VF,
@@ -2582,6 +2589,18 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
         end
       end
       // 2 source registers (rs1, rs2)
+      riscv_instr::MLE8_V_A,
+      riscv_instr::MLE8_V_B,
+      riscv_instr::MLE8_V_C,
+      riscv_instr::MLE16_V_A,
+      riscv_instr::MLE16_V_B,
+      riscv_instr::MLE16_V_C,
+      riscv_instr::MLE32_V_A,
+      riscv_instr::MLE32_V_B,
+      riscv_instr::MLE32_V_C,
+      riscv_instr::MLE64_V_A,
+      riscv_instr::MLE64_V_B,
+      riscv_instr::MLE64_V_C,
       riscv_instr::VLSE8_V,
       riscv_instr::VLSE16_V,
       riscv_instr::VLSE32_V,
@@ -2598,6 +2617,18 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
         end
       end
       // 2 source registers (rs1, rs2) and memory store opeeration
+      riscv_instr::MSE8_V_A,
+      riscv_instr::MSE8_V_B,
+      riscv_instr::MSE8_V_C,
+      riscv_instr::MSE16_V_A,
+      riscv_instr::MSE16_V_B,
+      riscv_instr::MSE16_V_C,
+      riscv_instr::MSE32_V_A,
+      riscv_instr::MSE32_V_B,
+      riscv_instr::MSE32_V_C,
+      riscv_instr::MSE64_V_A,
+      riscv_instr::MSE64_V_B,
+      riscv_instr::MSE64_V_C,
       riscv_instr::VSSE8_V,
       riscv_instr::VSSE16_V,
       riscv_instr::VSSE32_V,

hw/ip/spatz/src/generated/spatz_pkg.sv

@@ -68,6 +68,17 @@ package spatz_pkg;
   // Largest element width that Spatz supports
   localparam vew_e MAXEW = RVD ? EW_64 : EW_32;
 
+  //Number of Accumulator Banks
+  localparam int unsigned NrACCBanks = `ifdef N_ACC `N_ACC `else 16 `endif;
+
+  // MXU
+  localparam int unsigned MAX_TILE_M = 8;
+  localparam int unsigned MAX_TILE_N = 8;
+  // The col counter in the VLSU is parametrized on MAX_TILE_N only
+  // If you change this parameter, better parametrize the col counter
+  // in the VLSU as well
+  localparam int unsigned MAX_TILE_K = MAX_TILE_N;
+
   //////////////////////
   // Type Definitions //
   //////////////////////
@@ -89,6 +100,11 @@ package spatz_pkg;
   // Instruction ID
   typedef logic [$clog2(NrParallelInstructions)-1:0] spatz_id_t;
 
+  // MXU
+  typedef logic [$clog2(MAX_TILE_M):0] tile_m_t;
+  typedef logic [$clog2(MAX_TILE_N):0] tile_n_t;
+  typedef logic [$clog2(MAX_TILE_K):0] tile_k_t;
+
   /////////////////////
   // Operation Types //
   /////////////////////
@@ -109,6 +125,8 @@ package spatz_pkg;
     VMSEQ, VMSNE, VMSLTU, VMSLT, VMSLEU, VMSLE, VMSGTU, VMSGT,
     // Integer add-with-carry and subtract-with-borrow carry-out instructions
     VMADC, VMSBC,
+    // MXU Matrix multiplication and dot product instructions
+    MXMACC, MXFMACC,
     // Mask operations
     VMANDNOT, VMAND, VMOR, VMXOR, VMORNOT, VMNAND, VMNOR, VMXNOR,
     // Slide instructions
@@ -119,6 +137,8 @@ package spatz_pkg;
     VSE, VSSE, VSXE,
     // Config instruction
     VCFG,
+    // MXU Config instruction
+    MCFG,
     // VCSR
     VCSR,
     // Floating point instructions
@@ -150,6 +170,8 @@ package spatz_pkg;
     logic set_vstart;
     logic clear_vstart;
     logic reset_vstart;
+    // MXU
+    tile_dim_e dimTile;
   } op_cfg_t;
 
   typedef struct packed {
@@ -160,6 +182,10 @@ package spatz_pkg;
     logic vm;
     logic use_carry_borrow_in;
     logic is_scalar;
+
+    // MXU
+    logic is_mx;
+
     logic is_narrowing;
     logic is_reduction;
     logic switch_rs1_rd;
@@ -226,6 +252,12 @@ package spatz_pkg;
     vtype_t vtype;
     vlen_t vl;
     vlen_t vstart;
+
+    // MXU
+    tile_e matrix;
+    tile_m_t tile_M;
+    tile_n_t tile_N;
+    tile_k_t tile_K;
   } spatz_req_t;
 
   //////////////////////////////////

hw/ip/spatz/src/rvv_pkg.sv

@@ -36,6 +36,20 @@ package rvv_pkg;
     vlmul_e vlmul;
   } vtype_t;
 
+  // MXU
+  typedef enum logic [2:0] {
+    TILE_A = 3'b000,
+    TILE_B = 3'b001,
+    TILE_C = 3'b010
+  } tile_e;
+
+  // MXU
+  typedef enum logic [2:0] {
+    DIM_M = 3'b000,
+    DIM_N = 3'b001,
+    DIM_K = 3'b010
+  } tile_dim_e;
+
   ///////////////
   //  Opcodes  //
   ///////////////
@@ -51,4 +65,11 @@ package rvv_pkg;
     OPCFG = 3'b111
   } opcodev_func3_e;
 
+  // MXU
+  typedef enum logic [5:0] {
+    OPMVA = 6'b001001,
+    OPMVB = 6'b001010,
+    OPMVC = 6'b000000
+  } opcodev_func6_e;
+
  endpackage : rvv_pkg

hw/ip/spatz/src/spatz_controller.sv

@@ -77,17 +77,31 @@ module spatz_controller
   vlen_t  vstart_d, vstart_q;
   vlen_t  vl_d, vl_q;
   vtype_t vtype_d, vtype_q;
+  // MXU todo: is elen_t what we want?
+  elen_t tilem_d, tilem_q;
+  elen_t tilen_d, tilen_q;
+  elen_t tilek_d, tilek_q;
+
 
   `FF(vstart_q, vstart_d, '0)
   `FF(vl_q, vl_d, '0)
   `FF(vtype_q, vtype_d, '{vill: 1'b1, vsew: EW_8, vlmul: LMUL_1, default: '0})
 
+  // MXU
+  `FF(tilem_q, tilem_d, '0)
+  `FF(tilen_q, tilen_d, '0)
+  `FF(tilek_q, tilek_d, '0)
+
   always_comb begin : proc_vcsr
     automatic logic [$clog2(MAXVL):0] vlmax = 0;
 
     vstart_d = vstart_q;
     vl_d     = vl_q;
     vtype_d  = vtype_q;
+    // MXU
+    tilem_d  = tilem_q;
+    tilen_d  = tilen_q;
+    tilek_d  = tilek_q;
 
     if (spatz_req_valid) begin
       // Reset vstart to zero if we have a new non CSR operation
@@ -144,6 +158,12 @@ module spatz_controller
           end
         end
       end // spatz_req.op == VCFG
+      // MXU
+      if (spatz_req.op == MCFG) begin
+        tilem_d = spatz_req.op_cfg.dimTile == DIM_M ? spatz_req.rs1 : tilem_q;
+        tilen_d = spatz_req.op_cfg.dimTile == DIM_N ? spatz_req.rs1 : tilen_q;
+        tilek_d = spatz_req.op_cfg.dimTile == DIM_K ? spatz_req.rs1 : tilek_q;
+      end
     end // spatz_req_valid
   end
 
@@ -367,6 +387,9 @@ module spatz_controller
   // Retire CSR instruction and write back result to main core.
   logic retire_csr;
 
+  // Response to the scalar core
+  logic rsp_ready_q;
+
   // We stall issuing a new instruction if the corresponding execution unit is
   // not ready yet. Or we have a change in LMUL, for which we need to let all the
   // units finish first before scheduling a new operation (to avoid running into
@@ -392,7 +415,8 @@ module spatz_controller
   );
 
   // Pop the buffer if we do not have a unit stall
-  assign req_buffer_pop = ~stall & req_buffer_valid && !running_insn_full;
+  // Configuration instructions should wait until the core is ready to accept back the answer
+  assign req_buffer_pop = ~stall & (rsp_ready_q | (spatz_req.ex_unit != CON)) & req_buffer_valid && !running_insn_full;
 
   // Issue new operation to execution units
   always_comb begin : ex_issue
@@ -419,19 +443,38 @@ module spatz_controller
             spatz_req.vl     = 1;
             spatz_req.vstart = '0;
           end
+
+          // MXU
+          if (spatz_req.op_arith.is_mx) begin
+            spatz_req.tile_M = tilem_q;
+            spatz_req.tile_N = tilen_q;
+            spatz_req.tile_K = tilek_q;
+          end
         end
 
         LSU: begin
           // Overwrite vl and vstart in request (preserve vtype with vsew)
           spatz_req.vl     = vl_q;
           spatz_req.vstart = vstart_q;
+          // MXU
+          if (spatz_req.op_arith.is_mx) begin
+            spatz_req.tile_M = tilem_q;
+            spatz_req.tile_N = tilen_q;
+            spatz_req.tile_K = tilek_q;
+          end
         end
 
         SLD: begin
           // Overwrite all csrs in request
           spatz_req.vtype  = vtype_q;
           spatz_req.vl     = vl_q;
           spatz_req.vstart = vstart_q;
+          // MXU todo: check this, seems useless
+          if (spatz_req.op_arith.is_mx) begin
+            spatz_req.tile_M = tilem_q;
+            spatz_req.tile_N = tilen_q;
+            spatz_req.tile_K = tilek_q;
+          end
 
           // Is this a scalar request?
           if (spatz_req.op_arith.is_scalar) begin
@@ -529,7 +572,7 @@ module spatz_controller
     .ready_i(vfu_rsp_ready                  )
   );
 
-  logic       rsp_valid_d;
+  logic rsp_valid_d;
   spatz_rsp_t rsp_d;
   spill_register #(
     .T     (spatz_rsp_t ),
@@ -539,7 +582,7 @@ module spatz_controller
     .rst_ni (rst_ni      ),
     .data_i (rsp_d       ),
     .valid_i(rsp_valid_d ),
-    .ready_o(/* Unused */),
+    .ready_o(rsp_ready_q ),
     .data_o (rsp_o       ),
     .valid_o(rsp_valid_o ),
     .ready_i(rsp_ready_i )
@@ -568,6 +611,11 @@ module spatz_controller
             riscv_instr::CSR_VXSAT : rsp_d.data = '0;
             riscv_instr::CSR_VXRM  : rsp_d.data = '0;
             riscv_instr::CSR_VCSR  : rsp_d.data = '0;
+            // MXU
+            riscv_instr::CSR_MTYPE : rsp_d.data = '0;
+            riscv_instr::CSR_TILEM : rsp_d.data = elen_t'(tilem_q);
+            riscv_instr::CSR_TILEK : rsp_d.data = elen_t'(tilek_q);
+            riscv_instr::CSR_TILEN : rsp_d.data = elen_t'(tilen_q);
             default: rsp_d.data                 = '0;
           endcase
         end