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[spatz_controller] latch issue fix
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@Navaneeth-KunhiPurayil
Navaneeth-KunhiPurayil committed Nov 15, 2024
1 parent 15bca48 commit 1f915bd
Showing 1 changed file with 8 additions and 6 deletions.
14 changes: 8 additions & 6 deletions hw/ip/spatz/src/spatz_controller.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -250,8 +250,9 @@ module spatz_controller
`FF(done_result_q, done_result_d, '0)

// Counter to track the vlen completed for each instruction
vlen_t [NrParallelInstructions-1:0] vl_cnt_d, vl_cnt_q, vl_max;
vlen_t [NrParallelInstructions-1:0] vl_cnt_d, vl_cnt_q, vl_max_d, vl_max_q;
`FF(vl_cnt_q, vl_cnt_d, '0)
`FF(vl_max_q, vl_max_d, '0)

// Did the instruction write twice to the VRF in the previous two cycles?
logic [NrParallelInstructions-1:0] wrote_result_twice_d, wrote_result_twice_q;
Expand Down Expand Up @@ -279,6 +280,7 @@ module spatz_controller
done_result_d = done_result_q;
sb_enable_o = '0;
vl_cnt_d = vl_cnt_q;
vl_max_d = vl_max_q;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_controller.sv#L284 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/ip/spatz/src/spatz_controller.sv"  range:{start:{line:284  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:284  column:1}  end:{line:287}}  text:"\n      automatic logic intID;\n\n"}
for (int unsigned port = 0; port < NrVregfilePorts; port++) begin
// Calculate the load-store interface id to use here for chaining
Expand All @@ -291,7 +293,7 @@ module spatz_controller
intID = 1;
// For non vlsu ports, use the vector length to find the interface id for write status checks
end else begin
intID = (vl_cnt_q[sb_id_i[port]] < vl_max[sb_id_i[port]]) ? 0 : 1;
intID = (vl_cnt_q[sb_id_i[port]] < vl_max_d[sb_id_i[port]]) ? 0 : 1;
end

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[verible-verilog-lint] hw/ip/spatz/src/spatz_controller.sv#L298 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/ip/spatz/src/spatz_controller.sv"  range:{start:{line:298  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:298  column:1}  end:{line:299}}  text:"\n"}
// Enable the VRF port if the dependant instructions wrote in the previous cycle
Expand All @@ -301,9 +303,9 @@ module spatz_controller
// Store the decisions
if (sb_enable_o[SB_VFU_VD_WD]) begin
// Calculate the load-store interface id to use here for chaining
automatic logic intID = (vl_cnt_q[sb_id_i[SB_VFU_VD_WD]] < vl_max[sb_id_i[SB_VFU_VD_WD]]) ? 0 : 1;
automatic logic intID = (vl_cnt_q[sb_id_i[SB_VFU_VD_WD]] < vl_max_d[sb_id_i[SB_VFU_VD_WD]]) ? 0 : 1;
vl_cnt_d[sb_id_i[SB_VFU_VD_WD]] += VRFWordBWidth;
if (vl_cnt_q[sb_id_i[SB_VFU_VD_WD]] >= (vl_max[sb_id_i[SB_VFU_VD_WD]]-VRFWordBWidth)) begin
if (vl_cnt_q[sb_id_i[SB_VFU_VD_WD]] >= (vl_max_d[sb_id_i[SB_VFU_VD_WD]]-VRFWordBWidth)) begin
done_result_d[intID][sb_id_i[SB_VFU_VD_WD]] = 1'b1;
end

Expand All @@ -321,7 +323,7 @@ module spatz_controller
end
if (sb_enable_o[SB_VSLDU_VD_WD]) begin
// Calculate the load-store interface id to use here for chaining
automatic logic intID = (vl_cnt_q[sb_id_i[SB_VSLDU_VD_WD]] < vl_max[sb_id_i[SB_VSLDU_VD_WD]]) ? 0 : 1;
automatic logic intID = (vl_cnt_q[sb_id_i[SB_VSLDU_VD_WD]] < vl_max_d[sb_id_i[SB_VSLDU_VD_WD]]) ? 0 : 1;
vl_cnt_d[sb_id_i[SB_VSLDU_VD_WD]] += VRFWordBWidth;

wrote_result_narrowing_d[sb_id_i[SB_VSLDU_VD_WD]] = sb_wrote_result_i[SB_VSLDU_VD_WD - SB_VFU_VD_WD] ^ narrow_wide_q[sb_id_i[SB_VSLDU_VD_WD]];
Expand Down Expand Up @@ -421,7 +423,7 @@ module spatz_controller

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[verible-verilog-lint] hw/ip/spatz/src/spatz_controller.sv#L423 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/ip/spatz/src/spatz_controller.sv"  range:{start:{line:423  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:423  column:1}  end:{line:424}}  text:"\n"}
// Track request vl for vector chaining
// TODO: split the vector length here properly based on number of FPUs, EW, vstart, etc...
vl_max[spatz_req.id] = (spatz_req.vl >> 1) << spatz_req.vtype.vsew;
vl_max_d[spatz_req.id] = (spatz_req.vl >> 1) << spatz_req.vtype.vsew;
end

// An instruction never depends on itself
Expand Down

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