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occamy: Reduce the number of atomic IDs to one per cluster (#418)
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Co-authored-by: Samuel Riedel <[email protected]>
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@paulsc96 @SamuelRiedel
paulsc96 and SamuelRiedel authored May 27, 2022
1 parent 46c5fbe commit 6705170
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Showing 11 changed files with 655 additions and 654 deletions.
11 changes: 6 additions & 5 deletions hw/ip/snitch_cluster/src/snitch_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1014,9 +1014,10 @@ module snitch_cluster

reqrsp_req_t core_to_axi_req;
reqrsp_rsp_t core_to_axi_rsp;
logic [$clog2(NrCores)-1:0] core_req_idx;
user_t core_user;
assign core_user = hart_base_id_i + core_req_idx + 1'b1;
user_t cluster_user;
// Atomic ID, needs to be unique ID of cluster
// cluster_id + HartIdOffset + 1 (because 0 is for non-atomic masters)
assign cluster_user = (hart_base_id_i / NrCores) + (hart_base_id_i % NrCores) + 1'b1;

reqrsp_mux #(
.NrPorts (NrCores),
Expand All @@ -1032,7 +1033,7 @@ module snitch_cluster
.slv_rsp_o (filtered_core_rsp),
.mst_req_o (core_to_axi_req),
.mst_rsp_i (core_to_axi_rsp),
.idx_o (core_req_idx)
.idx_o (/*unused*/)
);

reqrsp_to_axi #(
Expand All @@ -1045,7 +1046,7 @@ module snitch_cluster
) i_reqrsp_to_axi_core (
.clk_i,
.rst_ni,
.user_i (core_user),
.user_i (cluster_user),
.reqrsp_req_i (core_to_axi_req),
.reqrsp_rsp_o (core_to_axi_rsp),
.axi_req_o (narrow_axi_mst_req[CoreReq]),
Expand Down
6 changes: 3 additions & 3 deletions hw/system/occamy/src/occamy_cfg.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@
rmq: 4,
}
narrow_xbar_slv_id_width: 4,
narrow_xbar_user_width: 8, // clog2(total number of cores)
narrow_xbar_user_width: 5, // clog2(total number of clusters)
nr_s1_quadrant: 6,
s1_quadrant: {
nr_clusters: 4,
Expand Down Expand Up @@ -121,7 +121,7 @@
fall_through: false,
},
narrow_xbar_slv_id_width: 4,
narrow_xbar_user_width: 8, // clog2(total number of cores)
narrow_xbar_user_width: 5, // clog2(total number of clusters)
cfg_base_addr: 184549376, // 0x0b000000
cfg_base_offset: 65536 // 0x10000
},
Expand All @@ -133,7 +133,7 @@
cluster_base_hartid: 1,
addr_width: 48,
data_width: 64,
user_width: 8, // clog2(total number of cores)
user_width: 5, // clog2(total number of clusters)
tcdm: {
size: 128, // 128 kiB
banks: 32,
Expand Down
2 changes: 1 addition & 1 deletion hw/system/occamy/src/occamy_cluster_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ package occamy_cluster_pkg;
localparam int unsigned WideIdWidthIn = 1;
localparam int unsigned WideIdWidthOut = $clog2(NrDmaMasters) + WideIdWidthIn;

localparam int unsigned NarrowUserWidth = 8;
localparam int unsigned NarrowUserWidth = 5;
localparam int unsigned WideUserWidth = 1;

localparam int unsigned ICacheLineWidth [NrHives] = '{
Expand Down
38 changes: 19 additions & 19 deletions hw/system/occamy/src/occamy_cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,26 +15,26 @@ module occamy_cva6
input logic ipi_i,
input logic time_irq_i,
input logic debug_req_i,
output axi_a48_d64_i4_u8_req_t axi_req_o,
input axi_a48_d64_i4_u8_resp_t axi_resp_i,
output axi_a48_d64_i4_u5_req_t axi_req_o,
input axi_a48_d64_i4_u5_resp_t axi_resp_i,
input sram_cfg_cva6_t sram_cfg_i
);

axi_a48_d64_i4_u8_req_t cva6_axi_req;
axi_a48_d64_i4_u8_resp_t cva6_axi_rsp;
axi_a48_d64_i4_u5_req_t cva6_axi_req;
axi_a48_d64_i4_u5_resp_t cva6_axi_rsp;

axi_a48_d64_i4_u8_req_t cva6_axi_cut_req;
axi_a48_d64_i4_u8_resp_t cva6_axi_cut_rsp;
axi_a48_d64_i4_u5_req_t cva6_axi_cut_req;
axi_a48_d64_i4_u5_resp_t cva6_axi_cut_rsp;

axi_multicut #(
.NoCuts(1),
.aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t),
.w_chan_t(axi_a48_d64_i4_u8_w_chan_t),
.b_chan_t(axi_a48_d64_i4_u8_b_chan_t),
.ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t),
.r_chan_t(axi_a48_d64_i4_u8_r_chan_t),
.axi_req_t(axi_a48_d64_i4_u8_req_t),
.axi_resp_t(axi_a48_d64_i4_u8_resp_t)
.aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t),
.w_chan_t(axi_a48_d64_i4_u5_w_chan_t),
.b_chan_t(axi_a48_d64_i4_u5_b_chan_t),
.ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t),
.r_chan_t(axi_a48_d64_i4_u5_r_chan_t),
.axi_req_t(axi_a48_d64_i4_u5_req_t),
.axi_resp_t(axi_a48_d64_i4_u5_resp_t)
) i_cva6_axi_cut (
.clk_i(clk_i),
.rst_ni(rst_ni),
Expand Down Expand Up @@ -130,12 +130,12 @@ module occamy_cva6
.AxiAddrWidth(48),
.AxiDataWidth(64),
.AxiIdWidth(4),
.AxiUserWidth(8),
.axi_ar_chan_t(axi_a48_d64_i4_u8_ar_chan_t),
.axi_aw_chan_t(axi_a48_d64_i4_u8_aw_chan_t),
.axi_w_chan_t(axi_a48_d64_i4_u8_w_chan_t),
.axi_req_t(axi_a48_d64_i4_u8_req_t),
.axi_rsp_t(axi_a48_d64_i4_u8_resp_t),
.AxiUserWidth(5),
.axi_ar_chan_t(axi_a48_d64_i4_u5_ar_chan_t),
.axi_aw_chan_t(axi_a48_d64_i4_u5_aw_chan_t),
.axi_w_chan_t(axi_a48_d64_i4_u5_w_chan_t),
.axi_req_t(axi_a48_d64_i4_u5_req_t),
.axi_rsp_t(axi_a48_d64_i4_u5_resp_t),
.sram_cfg_t(sram_cfg_t)
) i_cva6 (
.clk_i,
Expand Down
166 changes: 83 additions & 83 deletions hw/system/occamy/src/occamy_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -789,28 +789,28 @@ package occamy_pkg;
NoAddrRules: 20
};

// AXI bus with 48 bit address, 64 bit data, 4 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i4_u8, logic [47:0], logic [3:0], logic [63:0], logic [7:0],
logic [7:0])

// AXI bus with 48 bit address, 64 bit data, 8 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i8_u8, logic [47:0], logic [7:0], logic [63:0], logic [7:0],
logic [7:0])

typedef axi_a48_d64_i4_u8_req_t soc_narrow_xbar_in_req_t;
typedef axi_a48_d64_i8_u8_req_t soc_narrow_xbar_out_req_t;
typedef axi_a48_d64_i4_u8_resp_t soc_narrow_xbar_in_resp_t;
typedef axi_a48_d64_i8_u8_resp_t soc_narrow_xbar_out_resp_t;
typedef axi_a48_d64_i4_u8_aw_chan_t soc_narrow_xbar_in_aw_chan_t;
typedef axi_a48_d64_i8_u8_aw_chan_t soc_narrow_xbar_out_aw_chan_t;
typedef axi_a48_d64_i4_u8_w_chan_t soc_narrow_xbar_in_w_chan_t;
typedef axi_a48_d64_i8_u8_w_chan_t soc_narrow_xbar_out_w_chan_t;
typedef axi_a48_d64_i4_u8_b_chan_t soc_narrow_xbar_in_b_chan_t;
typedef axi_a48_d64_i8_u8_b_chan_t soc_narrow_xbar_out_b_chan_t;
typedef axi_a48_d64_i4_u8_ar_chan_t soc_narrow_xbar_in_ar_chan_t;
typedef axi_a48_d64_i8_u8_ar_chan_t soc_narrow_xbar_out_ar_chan_t;
typedef axi_a48_d64_i4_u8_r_chan_t soc_narrow_xbar_in_r_chan_t;
typedef axi_a48_d64_i8_u8_r_chan_t soc_narrow_xbar_out_r_chan_t;
// AXI bus with 48 bit address, 64 bit data, 4 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i4_u5, logic [47:0], logic [3:0], logic [63:0], logic [7:0],
logic [4:0])

// AXI bus with 48 bit address, 64 bit data, 8 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i8_u5, logic [47:0], logic [7:0], logic [63:0], logic [7:0],
logic [4:0])

typedef axi_a48_d64_i4_u5_req_t soc_narrow_xbar_in_req_t;
typedef axi_a48_d64_i8_u5_req_t soc_narrow_xbar_out_req_t;
typedef axi_a48_d64_i4_u5_resp_t soc_narrow_xbar_in_resp_t;
typedef axi_a48_d64_i8_u5_resp_t soc_narrow_xbar_out_resp_t;
typedef axi_a48_d64_i4_u5_aw_chan_t soc_narrow_xbar_in_aw_chan_t;
typedef axi_a48_d64_i8_u5_aw_chan_t soc_narrow_xbar_out_aw_chan_t;
typedef axi_a48_d64_i4_u5_w_chan_t soc_narrow_xbar_in_w_chan_t;
typedef axi_a48_d64_i8_u5_w_chan_t soc_narrow_xbar_out_w_chan_t;
typedef axi_a48_d64_i4_u5_b_chan_t soc_narrow_xbar_in_b_chan_t;
typedef axi_a48_d64_i8_u5_b_chan_t soc_narrow_xbar_out_b_chan_t;
typedef axi_a48_d64_i4_u5_ar_chan_t soc_narrow_xbar_in_ar_chan_t;
typedef axi_a48_d64_i8_u5_ar_chan_t soc_narrow_xbar_out_ar_chan_t;
typedef axi_a48_d64_i4_u5_r_chan_t soc_narrow_xbar_in_r_chan_t;
typedef axi_a48_d64_i8_u5_r_chan_t soc_narrow_xbar_out_r_chan_t;

// verilog_lint: waive parameter-name-style
localparam int SOC_NARROW_XBAR_IW_IN = 4;
Expand Down Expand Up @@ -846,20 +846,20 @@ package occamy_pkg;
NoAddrRules: 1
};

typedef axi_a48_d64_i8_u8_req_t quadrant_s1_ctrl_soc_to_quad_xbar_in_req_t;
typedef axi_a48_d64_i8_u8_req_t quadrant_s1_ctrl_soc_to_quad_xbar_out_req_t;
typedef axi_a48_d64_i8_u8_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_in_resp_t;
typedef axi_a48_d64_i8_u8_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_out_resp_t;
typedef axi_a48_d64_i8_u8_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_aw_chan_t;
typedef axi_a48_d64_i8_u8_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_aw_chan_t;
typedef axi_a48_d64_i8_u8_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_w_chan_t;
typedef axi_a48_d64_i8_u8_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_w_chan_t;
typedef axi_a48_d64_i8_u8_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_b_chan_t;
typedef axi_a48_d64_i8_u8_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_b_chan_t;
typedef axi_a48_d64_i8_u8_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_ar_chan_t;
typedef axi_a48_d64_i8_u8_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_ar_chan_t;
typedef axi_a48_d64_i8_u8_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_r_chan_t;
typedef axi_a48_d64_i8_u8_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_r_chan_t;
typedef axi_a48_d64_i8_u5_req_t quadrant_s1_ctrl_soc_to_quad_xbar_in_req_t;
typedef axi_a48_d64_i8_u5_req_t quadrant_s1_ctrl_soc_to_quad_xbar_out_req_t;
typedef axi_a48_d64_i8_u5_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_in_resp_t;
typedef axi_a48_d64_i8_u5_resp_t quadrant_s1_ctrl_soc_to_quad_xbar_out_resp_t;
typedef axi_a48_d64_i8_u5_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_aw_chan_t;
typedef axi_a48_d64_i8_u5_aw_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_aw_chan_t;
typedef axi_a48_d64_i8_u5_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_w_chan_t;
typedef axi_a48_d64_i8_u5_w_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_w_chan_t;
typedef axi_a48_d64_i8_u5_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_b_chan_t;
typedef axi_a48_d64_i8_u5_b_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_b_chan_t;
typedef axi_a48_d64_i8_u5_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_ar_chan_t;
typedef axi_a48_d64_i8_u5_ar_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_ar_chan_t;
typedef axi_a48_d64_i8_u5_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_in_r_chan_t;
typedef axi_a48_d64_i8_u5_r_chan_t quadrant_s1_ctrl_soc_to_quad_xbar_out_r_chan_t;

// verilog_lint: waive parameter-name-style
localparam int QUADRANT_S1_CTRL_SOC_TO_QUAD_XBAR_IW_IN = 8;
Expand Down Expand Up @@ -895,20 +895,20 @@ package occamy_pkg;
NoAddrRules: 1
};

typedef axi_a48_d64_i4_u8_req_t quadrant_s1_ctrl_quad_to_soc_xbar_in_req_t;
typedef axi_a48_d64_i4_u8_req_t quadrant_s1_ctrl_quad_to_soc_xbar_out_req_t;
typedef axi_a48_d64_i4_u8_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_in_resp_t;
typedef axi_a48_d64_i4_u8_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_out_resp_t;
typedef axi_a48_d64_i4_u8_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_aw_chan_t;
typedef axi_a48_d64_i4_u8_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_aw_chan_t;
typedef axi_a48_d64_i4_u8_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_w_chan_t;
typedef axi_a48_d64_i4_u8_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_w_chan_t;
typedef axi_a48_d64_i4_u8_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_b_chan_t;
typedef axi_a48_d64_i4_u8_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_b_chan_t;
typedef axi_a48_d64_i4_u8_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_ar_chan_t;
typedef axi_a48_d64_i4_u8_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_ar_chan_t;
typedef axi_a48_d64_i4_u8_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_r_chan_t;
typedef axi_a48_d64_i4_u8_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_r_chan_t;
typedef axi_a48_d64_i4_u5_req_t quadrant_s1_ctrl_quad_to_soc_xbar_in_req_t;
typedef axi_a48_d64_i4_u5_req_t quadrant_s1_ctrl_quad_to_soc_xbar_out_req_t;
typedef axi_a48_d64_i4_u5_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_in_resp_t;
typedef axi_a48_d64_i4_u5_resp_t quadrant_s1_ctrl_quad_to_soc_xbar_out_resp_t;
typedef axi_a48_d64_i4_u5_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_aw_chan_t;
typedef axi_a48_d64_i4_u5_aw_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_aw_chan_t;
typedef axi_a48_d64_i4_u5_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_w_chan_t;
typedef axi_a48_d64_i4_u5_w_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_w_chan_t;
typedef axi_a48_d64_i4_u5_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_b_chan_t;
typedef axi_a48_d64_i4_u5_b_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_b_chan_t;
typedef axi_a48_d64_i4_u5_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_ar_chan_t;
typedef axi_a48_d64_i4_u5_ar_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_ar_chan_t;
typedef axi_a48_d64_i4_u5_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_in_r_chan_t;
typedef axi_a48_d64_i4_u5_r_chan_t quadrant_s1_ctrl_quad_to_soc_xbar_out_r_chan_t;

// verilog_lint: waive parameter-name-style
localparam int QUADRANT_S1_CTRL_QUAD_TO_SOC_XBAR_IW_IN = 4;
Expand Down Expand Up @@ -1057,24 +1057,24 @@ package occamy_pkg;
NoAddrRules: 4
};

// AXI bus with 48 bit address, 64 bit data, 7 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i7_u8, logic [47:0], logic [6:0], logic [63:0], logic [7:0],
logic [7:0])

typedef axi_a48_d64_i4_u8_req_t narrow_xbar_quadrant_s1_in_req_t;
typedef axi_a48_d64_i7_u8_req_t narrow_xbar_quadrant_s1_out_req_t;
typedef axi_a48_d64_i4_u8_resp_t narrow_xbar_quadrant_s1_in_resp_t;
typedef axi_a48_d64_i7_u8_resp_t narrow_xbar_quadrant_s1_out_resp_t;
typedef axi_a48_d64_i4_u8_aw_chan_t narrow_xbar_quadrant_s1_in_aw_chan_t;
typedef axi_a48_d64_i7_u8_aw_chan_t narrow_xbar_quadrant_s1_out_aw_chan_t;
typedef axi_a48_d64_i4_u8_w_chan_t narrow_xbar_quadrant_s1_in_w_chan_t;
typedef axi_a48_d64_i7_u8_w_chan_t narrow_xbar_quadrant_s1_out_w_chan_t;
typedef axi_a48_d64_i4_u8_b_chan_t narrow_xbar_quadrant_s1_in_b_chan_t;
typedef axi_a48_d64_i7_u8_b_chan_t narrow_xbar_quadrant_s1_out_b_chan_t;
typedef axi_a48_d64_i4_u8_ar_chan_t narrow_xbar_quadrant_s1_in_ar_chan_t;
typedef axi_a48_d64_i7_u8_ar_chan_t narrow_xbar_quadrant_s1_out_ar_chan_t;
typedef axi_a48_d64_i4_u8_r_chan_t narrow_xbar_quadrant_s1_in_r_chan_t;
typedef axi_a48_d64_i7_u8_r_chan_t narrow_xbar_quadrant_s1_out_r_chan_t;
// AXI bus with 48 bit address, 64 bit data, 7 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i7_u5, logic [47:0], logic [6:0], logic [63:0], logic [7:0],
logic [4:0])

typedef axi_a48_d64_i4_u5_req_t narrow_xbar_quadrant_s1_in_req_t;
typedef axi_a48_d64_i7_u5_req_t narrow_xbar_quadrant_s1_out_req_t;
typedef axi_a48_d64_i4_u5_resp_t narrow_xbar_quadrant_s1_in_resp_t;
typedef axi_a48_d64_i7_u5_resp_t narrow_xbar_quadrant_s1_out_resp_t;
typedef axi_a48_d64_i4_u5_aw_chan_t narrow_xbar_quadrant_s1_in_aw_chan_t;
typedef axi_a48_d64_i7_u5_aw_chan_t narrow_xbar_quadrant_s1_out_aw_chan_t;
typedef axi_a48_d64_i4_u5_w_chan_t narrow_xbar_quadrant_s1_in_w_chan_t;
typedef axi_a48_d64_i7_u5_w_chan_t narrow_xbar_quadrant_s1_out_w_chan_t;
typedef axi_a48_d64_i4_u5_b_chan_t narrow_xbar_quadrant_s1_in_b_chan_t;
typedef axi_a48_d64_i7_u5_b_chan_t narrow_xbar_quadrant_s1_out_b_chan_t;
typedef axi_a48_d64_i4_u5_ar_chan_t narrow_xbar_quadrant_s1_in_ar_chan_t;
typedef axi_a48_d64_i7_u5_ar_chan_t narrow_xbar_quadrant_s1_out_ar_chan_t;
typedef axi_a48_d64_i4_u5_r_chan_t narrow_xbar_quadrant_s1_in_r_chan_t;
typedef axi_a48_d64_i7_u5_r_chan_t narrow_xbar_quadrant_s1_out_r_chan_t;

// verilog_lint: waive parameter-name-style
localparam int NARROW_XBAR_QUADRANT_S1_IW_IN = 4;
Expand All @@ -1085,9 +1085,9 @@ package occamy_pkg;
`APB_TYPEDEF_REQ_T(apb_a48_d32_req_t, logic [47:0], logic [31:0], logic [3:0])
`APB_TYPEDEF_RESP_T(apb_a48_d32_rsp_t, logic [31:0])

// AXI bus with 48 bit address, 32 bit data, 8 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d32_i8_u8, logic [47:0], logic [7:0], logic [31:0], logic [3:0],
logic [7:0])
// AXI bus with 48 bit address, 32 bit data, 8 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d32_i8_u5, logic [47:0], logic [7:0], logic [31:0], logic [3:0],
logic [4:0])

// Register bus with 48 bit address and 64 bit data.
`REG_BUS_TYPEDEF_ALL(reg_a48_d64, logic [47:0], logic [63:0], logic [7:0])
Expand All @@ -1096,21 +1096,21 @@ package occamy_pkg;
`AXI_TYPEDEF_ALL(axi_a48_d64_i4_u0, logic [47:0], logic [3:0], logic [63:0], logic [7:0],
logic [0:0])

// AXI bus with 48 bit address, 512 bit data, 4 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d512_i4_u8, logic [47:0], logic [3:0], logic [511:0], logic [63:0],
logic [7:0])
// AXI bus with 48 bit address, 512 bit data, 4 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d512_i4_u5, logic [47:0], logic [3:0], logic [511:0], logic [63:0],
logic [4:0])

// AXI bus with 48 bit address, 64 bit data, 1 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i1_u8, logic [47:0], logic [0:0], logic [63:0], logic [7:0],
logic [7:0])
// AXI bus with 48 bit address, 64 bit data, 1 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i1_u5, logic [47:0], logic [0:0], logic [63:0], logic [7:0],
logic [4:0])

// AXI bus with 48 bit address, 32 bit data, 1 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d32_i1_u8, logic [47:0], logic [0:0], logic [31:0], logic [3:0],
logic [7:0])
// AXI bus with 48 bit address, 32 bit data, 1 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d32_i1_u5, logic [47:0], logic [0:0], logic [31:0], logic [3:0],
logic [4:0])

// AXI bus with 48 bit address, 64 bit data, 2 bit IDs, and 8 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i2_u8, logic [47:0], logic [1:0], logic [63:0], logic [7:0],
logic [7:0])
// AXI bus with 48 bit address, 64 bit data, 2 bit IDs, and 5 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d64_i2_u5, logic [47:0], logic [1:0], logic [63:0], logic [7:0],
logic [4:0])

// AXI bus with 48 bit address, 512 bit data, 1 bit IDs, and 0 bit user data.
`AXI_TYPEDEF_ALL(axi_a48_d512_i1_u0, logic [47:0], logic [0:0], logic [511:0], logic [63:0],
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