Skip to content

Commit

Permalink
Add vsim bare test to CI
Browse files Browse the repository at this point in the history
micprog committed Aug 8, 2024
1 parent 728cbf9 commit 70b750a
Showing 3 changed files with 5 additions and 2 deletions.
3 changes: 3 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
@@ -19,6 +19,9 @@ test-vsim: scripts/compile.tcl
$(VSIM) -64 -c -do "quit -code [source scripts/compile.tcl]"
$(VSIM) -64 -do "vsim axi_memory_island_tb -voptargs=+acc; do scripts/debug_wave.do"

test-vsim-bare: scripts/compile.tcl
$(VSIM) -64 -c -do "quit -code [source scripts/compile.tcl]"
$(VSIM) -64 -c -do "vsim axi_memory_island_tb; run -all"

## Internal CI
NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/memory_island_nonfree.git
2 changes: 1 addition & 1 deletion test/axi_memory_island_tb.sv
Original file line number Diff line number Diff line change
@@ -696,7 +696,7 @@ module axi_memory_island_tb #(
errors += $countones(mismatch);
if (end_of_sim == '1) begin
$display("Counted %d errors.", errors);
$stop();
$finish(errors);
end
@(posedge clk);
end while (1'b1);
2 changes: 1 addition & 1 deletion test/synth/axi_memory_island_synth.sv
Original file line number Diff line number Diff line change
@@ -290,7 +290,7 @@ module axi_memory_island_synth #(
.SpillWideRspRouted (0),
.SpillWideReqSplit (0),
.SpillWideRspSplit (0),
.SpillReqBank (0),
.SpillReqBank (1),
.SpillRspBank (1),
.WidePriorityWait (2)
) i_mem_island (

0 comments on commit 70b750a

Please sign in to comment.