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Create a True Multiprotcol DMA Engine #22
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@@ -64,49 +53,24 @@ sources: | |||
- files: # 64bit descriptor frontend | |||
# Level 0 | |||
- src/frontends/desc64/idma_desc64_reg_pkg.sv | |||
# Level 1 |
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Create sub-bender files for the frontends and the systems. @thommythomaso
@@ -0,0 +1,182 @@ | |||
# Copyright 2022 ETH Zurich and University of Bologna. |
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This database format needs to be documented. Both in-file and in a dedicated md file.
// Tobias Senti <[email protected]> | ||
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/// A byte-granular buffer holding data while it is copied. | ||
module idma_dataflow_element #( |
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We also need to include the user signals discussed
@@ -0,0 +1,132 @@ | |||
// Copyright 2022 ETH Zurich and University of Bologna. |
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We should move this to common cells.
if (not_bursting_i) begin | ||
page_addr_width = OffsetWidth; | ||
end else begin | ||
// should the "virtual" page be reduced? e.g. the transfers split into |
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we can add this as a parameter, but tbh I don't think its too much worth.
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I would leave it in this first version
@@ -0,0 +1,74 @@ | |||
// Copyright 2022 ETH Zurich and University of Bologna. |
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We should replace this with a common cells implementation.
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I will do that.
@@ -0,0 +1,585 @@ | |||
#!/usr/env python3 |
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Add a bit more doc?
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Additional comments:
- Move stream fifo to the comment cells version
- Remove the axi submodule
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* treewide: Create a True Multiprotcol DMA Engine #22 * treewide: Various cleanup and moderinazion passes --------- Co-authored-by: Tobias Senti <[email protected]>
* treewide: Create a True Multiprotocol DMA Engine #22 * treewide: Various cleanup and modernization passes --------- Co-authored-by: Tobias Senti <[email protected]>
Thank @TheMightyDuckOfDoom for your contributions. It will be merged as part of #36. Closed. |
* treewide: Create a True Multiprotocol DMA Engine #22 * treewide: Various cleanup and modernization passes --------- Co-authored-by: Tobias Senti <[email protected]>
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