WIP Update python script to allow more register. Additionally align t…

…he iDMA conf and the sMMU conf register to 64 Bit.
pulp-platform · Dec 2, 2024 · 07ad957 · 07ad957
1 parent 837754d
commit 07ad957
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Showing 3 changed files with 18 additions and 10 deletions.
diff --git a/src/frontend/reg/tpl/idma_reg.hjson.tpl b/src/frontend/reg/tpl/idma_reg.hjson.tpl
@@ -55,14 +55,14 @@ ${params}
         }
       ]
     },
-    { name: "dummy_register",
-      desc: "Dummy Register to prevent that the core overwrites the smmu config register while writing the dma conf register!",
+    { name: "dummy_register_1",
+      desc: "Dummy Register to align for 64 bit! TODO: Update Driver to avoid writing 64 Bit!",
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0",
-          name: "dummy",
-          desc: "dummy flag"
+        { bits: "31:0",
+          name: "dummy_bits_1",
+          desc: "Dummy Bits"
         }
       ]
     },
@@ -89,6 +89,17 @@ ${params}
         }
       ]
     },
+    { name: "dummy_register_2",
+      desc: "Dummy Register to align for 64 bit! TODO: Update Driver to avoid writing 64 Bit!",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0",
+          name: "dummy_bits_2",
+          desc: "Dummy Bits"
+        }
+      ]
+    },
     { name: "smmu_root_pt_h",
       desc: "High Word of the root of the page table",
       swaccess: "rw",

diff --git a/src/frontend/reg/tpl/idma_reg.sv.tpl b/src/frontend/reg/tpl/idma_reg.sv.tpl
@@ -62,8 +62,6 @@ module idma_${identifier} #(
   logic     [NumRegs-1:0] arb_valid;
   logic     [NumRegs-1:0] arb_ready;
 
-  logic   dummy;
-
   // register signals
   reg_rsp_t [NumRegs-1:0] dma_ctrl_rsp;
 
@@ -141,7 +139,6 @@ module idma_${identifier} #(
       smmu_f_user           = dma_reg2hw[i].smmu.f_user.q;
       smmu_f_update_tlb     = dma_reg2hw[i].smmu.f_update_tlb.q;
       smmu_pt_root_adr      = {dma_reg2hw[i].smmu_root_pt_h.q , dma_reg2hw[i].smmu_root_pt_l.q};
-      dummy                 = dma_reg2hw[i].dummy_register.dummy.q;
 
 % if num_dim != 1:
       // ND connections

diff --git a/util/mario/frontend.py b/util/mario/frontend.py
@@ -72,7 +72,7 @@ def render_reg_hjson(fe_ids: dict, tpl_file: str) -> str:
         # higher register depends on the bit-width: 32-bit-case just add alignment marks
         if fe_ids[fe_id][0] == '32':
             for i in range(0, 3 * int(fe_ids[fe_id][1])):
-                align_regs.append(f'    {{ skipto: "{hex(8*i + 0xD0)}" }},\n')
+                align_regs.append(f'    {{ skipto: "{hex(8*i + 0xE0)}" }},\n')
 
             # assemble regs
             regs = low_regs + align_regs
@@ -107,7 +107,7 @@ def render_reg_hjson(fe_ids: dict, tpl_file: str) -> str:
             regs[1::2] = high_regs
 
             # render
-            regs = '    { skipto: "0xD0" },\n' + ''.join(regs)[:-2]
+            regs = '    { skipto: "0xE0" },\n' + ''.join(regs)[:-2]
 
         # unsupported bit width
         else: