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Fix lint.
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Yvan Tortorella committed May 9, 2024
1 parent e42703f commit a1bf0bc
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Showing 29 changed files with 184 additions and 178 deletions.
2 changes: 1 addition & 1 deletion core/axi_shim.sv
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Expand Up @@ -286,7 +286,7 @@ module axi_shim #(
// Registers
// ----------------
`FFARNC(wr_state_q, wr_state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(wr_cnt_q , wr_cnt_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(wr_cnt_q, wr_cnt_d, clear_i, '0, clk_i, rst_ni)

// ----------------
// Assertions
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16 changes: 8 additions & 8 deletions core/cache_subsystem/axi_adapter.sv
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Expand Up @@ -463,14 +463,14 @@ module axi_adapter #(
// ----------------
// Registers
// ----------------
`FFARNC(state_q , state_d , 1'b0, IDLE , clk_i, rst_ni)
`FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(cache_line_q , cache_line_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(addr_offset_q , addr_offset_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(id_q , id_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(amo_q , amo_d , 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni)
`FFARNC(size_q , size_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(outstanding_aw_cnt_q , outstanding_aw_cnt_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(state_q, state_d, 1'b0, IDLE, clk_i, rst_ni)
`FFARNC(cnt_q, cnt_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(cache_line_q, cache_line_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(addr_offset_q, addr_offset_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(id_q, id_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(amo_q, amo_d, 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni)
`FFARNC(size_q, size_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(outstanding_aw_cnt_q, outstanding_aw_cnt_d, 1'b0, '0, clk_i, rst_ni)

function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo);
axi_pkg::atop_t result = 6'b000000;
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6 changes: 3 additions & 3 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -444,9 +444,9 @@ module cache_ctrl
// --------------
// Registers
// --------------
`FFARNC(state_q , state_d , clear_i, IDLE, clk_i, rst_ni)
`FFARNC(mem_req_q , mem_req_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(hit_way_q , hit_way_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(mem_req_q, mem_req_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(hit_way_q, hit_way_d, clear_i, '0, clk_i, rst_ni)

//pragma translate_off
`ifndef VERILATOR
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2 changes: 1 addition & 1 deletion core/cache_subsystem/cva6_hpdcache_if_adapter.sv
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Expand Up @@ -111,7 +111,7 @@ module cva6_hpdcache_if_adapter
logic [ 7:0] amo_data_be;
hpdcache_req_op_t amo_op;
logic [31:0] amo_resp_word;
logic amo_pending_q, amo_pending_n;
logic amo_pending_q, amo_pending_n;

// AMO logic
// {{{
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20 changes: 10 additions & 10 deletions core/cache_subsystem/miss_handler.sv
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Expand Up @@ -507,12 +507,12 @@ module miss_handler
// --------------------
// Sequential Process
// --------------------
`FFARNC(mshr_q , mshr_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(state_q , state_d , 1'b0, INIT, clk_i, rst_ni)
`FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(evict_way_q , evict_way_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(evict_cl_q , evict_cl_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(serve_amo_q , serve_amo_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(mshr_q, mshr_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(state_q, state_d, 1'b0, INIT, clk_i, rst_ni)
`FFARNC(cnt_q, cnt_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(evict_way_q, evict_way_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(evict_cl_q, evict_cl_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(serve_amo_q, serve_amo_d, 1'b0, '0, clk_i, rst_ni)

//pragma translate_off
`ifndef VERILATOR
Expand Down Expand Up @@ -789,10 +789,10 @@ module axi_adapter_arbiter #(
endcase
end

`FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni)
`FFARNC(sel_q , sel_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(req_q , req_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(outstanding_cnt_q , outstanding_cnt_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(state_q, state_d, 1'b0, IDLE, clk_i, rst_ni)
`FFARNC(sel_q, sel_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(req_q, req_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(outstanding_cnt_q, outstanding_cnt_d, 1'b0, '0, clk_i, rst_ni)

// ------------
// Assertions
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28 changes: 14 additions & 14 deletions core/cache_subsystem/wt_axi_adapter.sv
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Expand Up @@ -621,20 +621,20 @@ module wt_axi_adapter
// assign dcache_rtrn_o.inv.vld = '0;
// assign dcache_rtrn_o.inv.all = '0;

`FFARNC(icache_first_q , icache_first_d , clear_i, 1'b1 , clk_i, rst_ni)
`FFARNC(dcache_first_q , dcache_first_d , clear_i, 1'b1 , clk_i, rst_ni)
`FFARNC(icache_rd_shift_q , icache_rd_shift_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(icache_rd_shift_user_q , icache_rd_shift_user_d, clear_i, '0 , clk_i, rst_ni)
`FFARNC(dcache_rd_shift_q , dcache_rd_shift_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(dcache_rd_shift_user_q , dcache_rd_shift_user_d, clear_i, '0 , clk_i, rst_ni)
`FFARNC(icache_rtrn_vld_q , icache_rtrn_vld_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_vld_q , dcache_rtrn_vld_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(icache_rtrn_tid_q , icache_rtrn_tid_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_tid_q , dcache_rtrn_tid_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_type_q , dcache_rtrn_type_d , clear_i, wt_cache_pkg::DCACHE_LOAD_ACK, clk_i, rst_ni)
`FFARNC(dcache_rtrn_inv_q , dcache_rtrn_inv_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(amo_off_q , amo_off_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(amo_gen_r_q , amo_gen_r_d , clear_i, '0 , clk_i, rst_ni)
`FFARNC(icache_first_q, icache_first_d, clear_i, 1'b1, clk_i, rst_ni)
`FFARNC(dcache_first_q, dcache_first_d, clear_i, 1'b1, clk_i, rst_ni)
`FFARNC(icache_rd_shift_q, icache_rd_shift_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(icache_rd_shift_user_q, icache_rd_shift_user_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dcache_rd_shift_q, dcache_rd_shift_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dcache_rd_shift_user_q, dcache_rd_shift_user_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(icache_rtrn_vld_q, icache_rtrn_vld_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dcache_rtrn_vld_q, dcache_rtrn_vld_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(icache_rtrn_tid_q, icache_rtrn_tid_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dcache_rtrn_tid_q, dcache_rtrn_tid_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dcache_rtrn_type_q, dcache_rtrn_type_d, clear_i, wt_cache_pkg::DCACHE_LOAD_ACK, clk_i, rst_ni)
`FFARNC(dcache_rtrn_inv_q, dcache_rtrn_inv_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(amo_off_q, amo_off_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(amo_gen_r_q, amo_gen_r_d, clear_i, '0, clk_i, rst_ni)


///////////////////////////////////////////////////////
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5 changes: 2 additions & 3 deletions core/cache_subsystem/wt_dcache.sv
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Expand Up @@ -24,9 +24,8 @@ module wt_dcache
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clear_i, // Synchronous clear active high

input logic rst_ni, // Asynchronous reset active low
input logic clear_i, // Synchronous clear active high
// Cache management
input logic enable_i, // from CSR
input logic flush_i, // high until acknowledged
Expand Down
12 changes: 6 additions & 6 deletions core/cache_subsystem/wt_dcache_mem.sv
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Expand Up @@ -342,10 +342,10 @@ module wt_dcache_mem
);
end

`FFARNC(bank_idx_q , bank_idx_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(bank_off_q , bank_off_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(vld_sel_q , vld_sel_d , 1'b0, '0, clk_i, rst_ni)
`FFARNC(cmp_en_q , cmp_en_d , 1'b0, '0, clk_i, rst_ni)
`FFARNC(bank_idx_q, bank_idx_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(bank_off_q, bank_off_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(vld_sel_q, vld_sel_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(cmp_en_q, cmp_en_d, 1'b0, '0, clk_i, rst_ni)

///////////////////////////////////////////////////////
// assertions
Expand Down Expand Up @@ -395,8 +395,8 @@ module wt_dcache_mem
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] load_enable;
for (genvar i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin : gen_p_mirror_registers
assign load_enable[i] = (vld_req[i] & vld_we) ? 1'b1 : 1'b0;
`FFLARNC(vld_mirror[vld_addr][i], vld_wdata[i], load_enable[i], clear_i, '{default: '0}, clk_i, rst_ni)
`FFLARNC(tag_mirror[vld_addr][i], wr_cl_tag_i, load_enable[i], clear_i, '{default: '0}, clk_i, rst_ni)
`FFLARNC(vld_mirror[vld_addr][i], vld_wdata[i], load_enable[i], clear_i, '0, clk_i, rst_ni)
`FFLARNC(tag_mirror[vld_addr][i], wr_cl_tag_i, load_enable[i], clear_i, '0, clk_i, rst_ni)
end

for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : gen_tag_dubl_test
Expand Down
6 changes: 3 additions & 3 deletions core/cache_subsystem/wt_dcache_wbuffer.sv
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Expand Up @@ -56,9 +56,9 @@ module wt_dcache_wbuffer
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clear_i, // Synchronous clear active high
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low
input logic clear_i, // synchronous clear active high

input logic cache_en_i, // writes are treated as NC if disabled
output logic empty_o, // asserted if no data is present in write buffer
Expand Down
4 changes: 2 additions & 2 deletions core/cvxif_fu.sv
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Expand Up @@ -117,8 +117,8 @@ module cvxif_fu
end
end

`FFARNC(illegal_q , illegal_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(illegal_id_q , illegal_id_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(illegal_q, illegal_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(illegal_id_q, illegal_id_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(illegal_instr_q, illegal_instr_n, clear_i, '0, clk_i, rst_ni)

endmodule
30 changes: 19 additions & 11 deletions core/ex_stage.sv
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Expand Up @@ -348,7 +348,7 @@ module ex_stage
) i_mult (
.clk_i,
.rst_ni,
.clear_i(clear_i),
.clear_i,
.flush_i,
.mult_valid_i,
.fu_data_i (mult_data),
Expand Down Expand Up @@ -510,26 +510,34 @@ module ex_stage

if (CVA6Cfg.RVS) begin
if (CVA6Cfg.RVH) begin
`FFLARNC(current_instruction_is_sfence_vma , 1'b1, load_enable[0], clear_i, 1'b0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_hfence_vvma, 1'b1, load_enable[1], clear_i, 1'b0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_hfence_gvma, 1'b1, load_enable[2], clear_i, 1'b0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[0], clear_i, '0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_hfence_vvma, '1, load_enable[1], clear_i, '0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_hfence_gvma, '1, load_enable[2], clear_i, '0, clk_i, rst_ni)
end else begin
assign current_instruction_is_hfence_vvma = 1'b0;
assign current_instruction_is_hfence_gvma = 1'b0;
`FFLARNC(current_instruction_is_sfence_vma, 1'b1, load_enable[3], clear_i, 1'b0, clk_i, rst_ni)
`FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[3], clear_i, '0, clk_i, rst_ni)
end
if (CVA6Cfg.RVH) begin
logic [ASID_WIDTH-1:0] asid_rs2_forwarding;
logic [VMID_WIDTH-1:0] vmid_rs2_forwarding;
logic [riscv::GPLEN-1:0] gpaddr_flush;
assign asid_rs2_forwarding = rs2_forwarding_i[ASID_WIDTH-1:0];
assign vmid_rs2_forwarding = rs2_forwarding_i[VMID_WIDTH-1:0];
assign gpaddr_flush = rs1_forwarding_i >> 2;
// This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
`FFLARNC(vaddr_to_be_flushed , rs1_forwarding_i , load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(gpaddr_to_be_flushed, rs1_forwarding_i >> 2 , load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(asid_to_be_flushed , rs2_forwarding_i[ASID_WIDTH-1:0], load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(vmid_to_be_flushed , rs2_forwarding_i[VMID_WIDTH-1:0], load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i, load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(gpaddr_to_be_flushed, gpaddr_flush, load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(asid_to_be_flushed, asid_rs2_forwarding, load_enable[4], clear_i, '0, clk_i, rst_ni)
`FFLARNC(vmid_to_be_flushed, vmid_rs2_forwarding, load_enable[4], clear_i, '0, clk_i, rst_ni)
end else begin
logic [ASID_WIDTH-1:0] asid_rs2_forwarding;
assign vmid_to_be_flushed = '0;
assign gpaddr_to_be_flushed = '0;
assign asid_rs2_forwarding = rs2_forwarding_i[ASID_WIDTH-1:0];
// This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
`FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i , load_enable[5], clear_i, '0, clk_i, rst_ni)
`FFLARNC(asid_to_be_flushed , rs2_forwarding_i[ASID_WIDTH-1:0], load_enable[5], clear_i, '0, clk_i, rst_ni)
`FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i, load_enable[5], clear_i, '0, clk_i, rst_ni)
`FFLARNC(asid_to_be_flushed, asid_rs2_forwarding, load_enable[5], clear_i, '0, clk_i, rst_ni)
end
end else begin
assign current_instruction_is_sfence_vma = 1'b0;
Expand Down
2 changes: 1 addition & 1 deletion core/frontend/frontend.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -461,7 +461,7 @@ module frontend
) i_ras (
.clk_i,
.rst_ni,
.clear_i (clear_i),
.clear_i,
.flush_i(flush_bp_i),
.push_i (ras_push),
.pop_i (ras_pop),
Expand Down
1 change: 0 additions & 1 deletion core/issue_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -166,7 +166,6 @@ module issue_stage
.CVA6Cfg (CVA6Cfg),
.rs3_len_t(rs3_len_t)
) i_scoreboard (
.clear_i(clear_i),
.rst_ni(rst_uarch_ni),

.sb_full_o (sb_full_o),
Expand Down
6 changes: 3 additions & 3 deletions core/load_store_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -331,9 +331,9 @@ module load_store_unit
assign dtlb_ppn = mmu_vaddr_plen[riscv::PLEN-1:12];
assign dtlb_hit = 1'b1;

`FFARNC(mmu_paddr , mmu_vaddr_plen , clear_i, '0, clk_i, rst_ni)
`FFARNC(translation_valid, translation_req , clear_i, '0, clk_i, rst_ni)
`FFARNC(mmu_exception , misaligned_exception, clear_i, '0, clk_i, rst_ni)
`FFARNC(mmu_paddr, mmu_vaddr_plen, clear_i, '0, clk_i, rst_ni)
`FFARNC(translation_valid, translation_req, clear_i, '0, clk_i, rst_ni)
`FFARNC(mmu_exception, misaligned_exception, clear_i, '0, clk_i, rst_ni)
end


Expand Down
8 changes: 4 additions & 4 deletions core/lsu_bypass.sv
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Expand Up @@ -117,9 +117,9 @@ module lsu_bypass
end

// registers
`FFARNC(mem_q , mem_n , 1'b0, '0, clk_i, rst_ni)
`FFARNC(status_cnt_q , status_cnt_n , 1'b0, '0, clk_i, rst_ni)
`FFARNC(write_pointer_q , write_pointer_n, 1'b0, '0, clk_i, rst_ni)
`FFARNC(read_pointer_q , read_pointer_n , 1'b0, '0, clk_i, rst_ni)
`FFARNC(mem_q, mem_n, 1'b0, '0, clk_i, rst_ni)
`FFARNC(status_cnt_q, status_cnt_n, 1'b0, '0, clk_i, rst_ni)
`FFARNC(write_pointer_q, write_pointer_n, 1'b0, '0, clk_i, rst_ni)
`FFARNC(read_pointer_q, read_pointer_n, 1'b0, '0, clk_i, rst_ni)
endmodule

16 changes: 8 additions & 8 deletions core/mmu_sv32/cva6_mmu_sv32.sv
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Expand Up @@ -122,7 +122,7 @@ module cva6_mmu_sv32
) i_itlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
.clear_i(clear_i),
.flush_i(flush_tlb_i),

.update_i(update_itlb),
Expand Down Expand Up @@ -571,11 +571,11 @@ module cva6_mmu_sv32
// ----------
// Registers
// ----------
`FFARNC(lsu_vaddr_q ,lsu_vaddr_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(lsu_req_q ,lsu_req_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(misaligned_ex_q ,misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_pte_q ,dtlb_pte_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_hit_q ,dtlb_hit_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(lsu_is_store_q ,lsu_is_store_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_is_4M_q ,dtlb_is_4M_n , clear_i, '0, clk_i, rst_ni)
`FFARNC(lsu_vaddr_q, lsu_vaddr_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(lsu_req_q, lsu_req_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(misaligned_ex_q, misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_pte_q, dtlb_pte_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_hit_q, dtlb_hit_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(lsu_is_store_q, lsu_is_store_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_is_4M_q, dtlb_is_4M_n, clear_i, '0, clk_i, rst_ni)
endmodule
20 changes: 10 additions & 10 deletions core/mmu_sv32/cva6_ptw_sv32.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -373,16 +373,16 @@ module cva6_ptw_sv32
end

// sequential process
`FFARNC(state_q , state_d , clear_i, IDLE, clk_i, rst_ni)
`FFARNC(ptw_pptr_q , ptw_pptr_n , clear_i, '0 , clk_i, rst_ni)
`FFARNC(is_instr_ptw_q , is_instr_ptw_n , clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(ptw_lvl_q , ptw_lvl_n , clear_i, LVL1, clk_i, rst_ni)
`FFARNC(tag_valid_q , tag_valid_n , clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(tlb_update_asid_q , tlb_update_asid_n , clear_i, '0 , clk_i, rst_ni)
`FFARNC(vaddr_q , vaddr_n , clear_i, '0 , clk_i, rst_ni)
`FFARNC(global_mapping_q , global_mapping_n , clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(data_rdata_q , req_port_i.data_rdata , clear_i, '0 , clk_i, rst_ni)
`FFARNC(data_rvalid_q , req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
`FFARNC(ptw_pptr_q, ptw_pptr_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(is_instr_ptw_q, is_instr_ptw_n, clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(ptw_lvl_q, ptw_lvl_n, clear_i, LVL1, clk_i, rst_ni)
`FFARNC(tag_valid_q, tag_valid_n, clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(tlb_update_asid_q, tlb_update_asid_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(vaddr_q, vaddr_n, clear_i, '0, clk_i, rst_ni)
`FFARNC(global_mapping_q, global_mapping_n, clear_i, 1'b0, clk_i, rst_ni)
`FFARNC(data_rdata_q, req_port_i.data_rdata, clear_i, '0, clk_i, rst_ni)
`FFARNC(data_rvalid_q, req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)

endmodule
/* verilator lint_on WIDTH */
26 changes: 13 additions & 13 deletions core/mmu_sv32/cva6_shared_tlb_sv32.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ module cva6_shared_tlb_sv32
parameter int SHARED_TLB_WAYS = 2,
parameter int ASID_WIDTH = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic clk_i, // clock
input logic rst_ni , // asynchronous reset active low
input logic clear_i,
input logic flush_i,

Expand Down Expand Up @@ -232,17 +232,17 @@ module cva6_shared_tlb_sv32
end //tag_comparison

// sequential process
`FFARNC(itlb_vpn_q , itlb_vaddr_i[riscv::SV-1:12] , clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_vpn_q , dtlb_vaddr_i[riscv::SV-1:12] , clear_i, '0, clk_i, rst_ni)
`FFARNC(tlb_update_asid_q , tlb_update_asid_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tlb_access_q , shared_tlb_access_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tlb_vaddr_q , shared_tlb_vaddr_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tag_valid_q , shared_tag_valid_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(vpn0_q , vpn0_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(vpn1_q , vpn1_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(itlb_req_q , itlb_req_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_req_q , dtlb_req_d , clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tag_valid , shared_tag_valid_q[tag_rd_addr], clear_i, '0, clk_i, rst_ni)
`FFARNC(itlb_vpn_q, itlb_vaddr_i[riscv::SV-1:12], clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_vpn_q, dtlb_vaddr_i[riscv::SV-1:12], clear_i, '0, clk_i, rst_ni)
`FFARNC(tlb_update_asid_q, tlb_update_asid_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tlb_access_q, shared_tlb_access_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tlb_vaddr_q, shared_tlb_vaddr_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tag_valid_q, shared_tag_valid_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(vpn0_q, vpn0_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(vpn1_q, vpn1_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(itlb_req_q, itlb_req_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(dtlb_req_q, dtlb_req_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(shared_tag_valid, shared_tag_valid_q[tag_rd_addr], clear_i, '0, clk_i, rst_ni)

// ------------------
// Update and Flush
Expand Down
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