Skip to content

Commit

Permalink
Merge pull request openhwgroup#87 from pulp-platform/aottaviano/vario…
Browse files Browse the repository at this point in the history 
…us-1

Various fixes - 1
  • Loading branch information
@alex96295
alex96295 authored Jul 12, 2023
2 parents 63ac4ab + 4e044fe commit b8b13ee
Show file tree
Hide file tree
Showing 4 changed files with 78 additions and 60 deletions.
42 changes: 21 additions & 21 deletions hw/carfield.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -185,7 +185,7 @@ logic car_can_intr;
// Propagate edge-triggered interrupts between periph and host clock domains

// Advanced timer
for (genvar i=0; i < 3; i++) begin : gen_sync_adv_timer_intrs
for (genvar i=0; i < CarfieldNumAdvTimerIntrs; i++) begin : gen_sync_adv_timer_intrs
edge_propagator i_sync_adv_timer_intrs (
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
Expand All @@ -196,7 +196,7 @@ for (genvar i=0; i < 3; i++) begin : gen_sync_adv_timer_intrs
);
end

for (genvar i=0; i < 3; i++) begin : gen_sync_adv_timer_events
for (genvar i=0; i < CarfieldNumAdvTimerEvents; i++) begin : gen_sync_adv_timer_events
edge_propagator i_sync_adv_timer_events (
.clk_tx_i ( periph_clk ),
.rstn_tx_i ( periph_pwr_on_rst_n ),
Expand Down Expand Up @@ -414,7 +414,7 @@ localparam int unsigned LlcWWidth = (2**LogDepth)*
logic hyper_isolate_req, hyper_isolated_rsp;
logic secd_isolate_req;

logic [iomsb(Cfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated;
logic [iomsb(Cfg.AxiExtNumSlv-1):0] slave_isolate_req, slave_isolated_rsp, slave_isolated;
logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp;

logic [LlcArWidth-1:0] llc_ar_data;
Expand All @@ -433,24 +433,24 @@ logic [ LlcWWidth-1:0] llc_w_data;
logic [ LogDepth:0] llc_w_wptr;
logic [ LogDepth:0] llc_w_rptr;

// All AXI Slaves (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_rptr ;

// All AXI Slaves (except the Integer Cluster)
// All AXI Slaves (except the Integer Cluster and the Mailbox)
logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_rptr ;

// All AXI Masters (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_rptr;
Expand Down
24 changes: 14 additions & 10 deletions hw/carfield_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,8 @@ typedef enum byte_bt {
EthernetSlvIdx = 'd3,
PeriphsSlvIdx = 'd4,
FPClusterSlvIdx = 'd5,
MailboxSlvIdx = 'd6,
IntClusterSlvIdx = 'd7
IntClusterSlvIdx = 'd6,
MailboxSlvIdx = 'd7
} axi_slv_idx_t;

typedef enum byte_bt {
Expand Down Expand Up @@ -83,8 +83,12 @@ typedef enum doub_bt {
} axi_end_t;

// APB peripherals
localparam int unsigned CarfieldNumTimerIntrs = 10; // 4 adv timer intrs, 4 adv timer events, 2 sys
// timer intrs

localparam int unsigned CarfieldNumAdvTimerIntrs = 4;
localparam int unsigned CarfieldNumAdvTimerEvents = 4;
localparam int unsigned CarfieldNumSysTimerIntrs = 2;
localparam int unsigned CarfieldNumTimerIntrs = CarfieldNumAdvTimerIntrs +
CarfieldNumAdvTimerEvents + CarfieldNumSysTimerIntrs;
localparam int unsigned CarfieldNumWdtIntrs = 5;
localparam int unsigned CarfieldNumCanIntrs = 1;
localparam int unsigned CarfieldNumPeriphsIntrs = CarfieldNumTimerIntrs +
Expand Down Expand Up @@ -227,27 +231,27 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
AxiExtNumSlv : AxiNumExtSlv,
AxiExtNumRules : AxiNumExtSlv,
// External AXI region map
AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterSlvIdx ,
AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxSlvIdx ,
IntClusterSlvIdx ,
FPClusterSlvIdx ,
PeriphsSlvIdx ,
EthernetSlvIdx ,
MailboxSlvIdx ,
SafetyIslandSlvIdx,
L2Port2SlvIdx ,
L2Port1SlvIdx },
AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterBase ,
AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxBase ,
IntClusterBase ,
FPClusterBase ,
PeriphsBase ,
EthernetBase ,
MailboxBase ,
SafetyIslandBase,
L2Port2Base ,
L2Port1Base },
AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterEnd ,
AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxEnd ,
IntClusterEnd ,
FPClusterEnd ,
PeriphsEnd ,
EthernetEnd ,
MailboxEnd ,
SafetyIslandEnd,
L2Port2End ,
L2Port1End },
Expand Down
49 changes: 26 additions & 23 deletions hw/cheshire_wrap.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -182,25 +182,26 @@ module cheshire_wrap
output logic [ LlcWWidth-1:0] llc_mst_w_data_o ,
output logic [ LogDepth:0] llc_mst_w_wptr_o ,
input logic [ LogDepth:0] llc_mst_w_rptr_i ,
// External AXI slave devices (except the Integer Cluster)
input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i,
output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_ar_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_ar_rptr_i,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_aw_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_aw_rptr_i,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_b_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_b_rptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_r_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_r_rptr_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_w_wptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_w_rptr_i ,
// External AXI master devices (except the Integer Cluster)
// External AXI isolate slave Ports (except the Mailbox)
input logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolate_i,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolated_o,
// External async AXI slave Ports (except the Integer Cluster and the Mailbox)
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_rptr_i,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_rptr_i,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_rptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_rptr_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_wptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_rptr_i ,
// External async AXI master Ports (except the Integer Cluster)
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i,
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_wptr_i,
output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_rptr_o,
Expand All @@ -216,7 +217,7 @@ module cheshire_wrap
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i ,
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_rptr_o ,
// Integer Cluster Slave Port
// Integer Cluster async Slave Port
output logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data_o,
output logic [ LogDepth:0] axi_slv_intcluster_aw_wptr_o,
input logic [ LogDepth:0] axi_slv_intcluster_aw_rptr_i,
Expand All @@ -232,7 +233,7 @@ module cheshire_wrap
input logic [ IntClusterAxiSlvRWidth-1:0] axi_slv_intcluster_r_data_i ,
input logic [ LogDepth:0] axi_slv_intcluster_r_wptr_i ,
output logic [ LogDepth:0] axi_slv_intcluster_r_rptr_o ,
// Integer Cluster Master Port
// Integer Cluster async Master Port
input logic [IntClusterAxiMstAwWidth-1:0] axi_mst_intcluster_aw_data_i,
input logic [ LogDepth:0] axi_mst_intcluster_aw_wptr_i,
output logic [ LogDepth:0] axi_mst_intcluster_aw_rptr_o,
Expand Down Expand Up @@ -441,7 +442,8 @@ cheshire_soc #(
.vga_blue_o
);

// Cheshire's AXI master cdc and isolate generation, but integer cluster and mailboxes
// Cheshire's AXI master cdc generation, except for the Integer Cluster (slave 6) and the Mailbox
// (slave 7)
for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc
axi_isolate #(
.NumPending ( Cfg.AxiMaxSlvTrans ),
Expand Down Expand Up @@ -498,7 +500,8 @@ for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc
);
end

// Cheshire's AXI slave cdc and isolate generation, but integer cluster

// Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7)
for (genvar i = 0; i < Cfg.AxiExtNumMst - 1; i++) begin: gen_ext_mst_dst_cdc
axi_cdc_dst #(
.LogDepth ( LogDepth ),
Expand Down
23 changes: 17 additions & 6 deletions tb/carfield_fix.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,8 +67,6 @@ module carfield_soc_fixture;

logic uart_tx;
logic uart_rx;
logic ot_uart_tx;
logic ot_uart_rx;

logic i2c_sda_o;
logic i2c_sda_i;
Expand Down Expand Up @@ -149,32 +147,45 @@ module carfield_soc_fixture;
.jtag_safety_island_tms_i ( '0 ), // Temporary
.jtag_safety_island_tdi_i ( '0 ), // Temporary
.jtag_safety_island_tdo_o ( jtag_safed_tdo ),
.bootmode_ot_i ( '0 ), // Temporary
.bootmode_safe_isln_i ( '0 ), // Temporary
.uart_tx_o ( uart_tx ),
.uart_rx_i ( uart_rx ),
.uart_ot_tx_o ( ot_uart_tx ),
.uart_ot_rx_i ( ot_uart_rx ),
.uart_ot_tx_o ( ),
.uart_ot_rx_i ( '0 ),
.i2c_sda_o ( i2c_sda_o ),
.i2c_sda_i ( i2c_sda_i ),
.i2c_sda_en_o ( i2c_sda_en ),
.i2c_scl_o ( i2c_scl_o ),
.i2c_scl_i ( i2c_scl_i ),
.i2c_scl_en_o ( i2c_scl_en ),
// hostd spi
.spih_sck_o ( spih_sck_o ),
.spih_sck_en_o ( spih_sck_en ),
.spih_csb_o ( spih_csb_o ),
.spih_csb_en_o ( spih_csb_en ),
.spih_sd_o ( spih_sd_o ),
.spih_sd_en_o ( spih_sd_en ),
.spih_sd_i ( spih_sd_i ),
// secd spi
.spih_ot_sck_o ( ),
.spih_ot_sck_en_o ( ),
.spih_ot_csb_o ( ),
.spih_ot_csb_en_o ( ),
.spih_ot_sd_o ( ),
.spih_ot_sd_en_o ( ),
.spih_ot_sd_i ( '0 ),
.eth_rxck_i ( '0 ),
.eth_rxctl_i ( '0 ),
.eth_rxd_i ( '0 ),
.eth_md_i ( '0 ),
.eth_txck_o ( /* Currently unconnected, tie to 0 */ ),
.eth_txctl_o ( /* Currently unconnected, tie to 0 */ ),
.eth_txd_o ( /* Currently unconnected, tie to 0 */ ),
.eth_md_o ( /* Currently unconnected, tie to 0 */ ),
.eth_md_oe ( /* Currently unconnected, tie to 0 */ ),
.eth_mdc_o ( /* Currently unconnected, tie to 0 */ ),
.eth_rst_n_o ( /* Currently unconnected, tie to 0 */ ),
.can_rx_i ( '0 ),
.can_tx_o ( ),
.gpio_i ( '0 ),
.gpio_o ( ),
.gpio_en_o ( ),
Expand Down

0 comments on commit b8b13ee

Please sign in to comment.