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Avoid wide signals in sensitivity lists of immediate assertions #229
Avoid wide signals in sensitivity lists of immediate assertions #229
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@michael-platzer Thanks for reporting this. With what Verilator version did you observe the failure? |
@colluca With version 5.018:
I have not tested it with the latest version though. Do you happen to use a newer version for which these are handled correctly? |
Update: I tested the current code from
Maybe this is just Verilator not properly supporting these complex assertions, but it could also be an indication there is something wrong and in need of fixing. @WRoenninger Could you please have a look? |
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I did some investigation with @WRoenninger and we found that Verilator has issues with wide signals in sensitivity lists. With the latest version (5.028) all issues can be resolved by using |
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LGTM, thanks @michael-platzer :)
Verilator has decent support for various types of assertions by now but dislikes wide signals (e.g., wider than 64 bits) in sensitivity lists.
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Changed |
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Thank you @michael-platzer @WRoenninger for getting to the bottom of this!
The
addr_decode_dync
andmultiaddr_decode
modules feature some complex assertions (actuallyassume
s to be precise) that are quite complex — too complex for Verilator it seems, which fails in unpredictable ways when these modules are present. Therefore, this PR disables those assertions in Verilator (based on whether theVERILATOR
pre-processor macro is defined).