Fix tool issues with automatic variables in PLRU tree #205
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Verilator currently does not properly support automatic variables declared inside a combinatorial block if these are only used in some branches (it incorrectly emits a latch warning for these variables). This PR moves the update logic and the PLRU output logic in
plru_tree.sv
into two functions to avoid this issue.Additionally, some linting tools (e.g. Spyglass) complain when individual bits of integers are accessed via indexing (as is commonly done with logic vectors), which occurs within the current implementation of
plru_tree.sv
in two instances, e.g.:common_cells/src/plru_tree.sv
Line 94 in 52f83ee
Instead of extracting bit 0 of
new_index
by indexing (i.e., vianew_index[0]
) this PR casts the integer to a width of 1 (via1'(new_index)
) instead, which is equivalent but does not cause linting issues.The code is otherwise unchanged and remains logically and functionally equivalent.