Replace all asserts & assumes with macros from assertions.svh
#262
collucaAnnotations
2 errors and 10 warnings
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Verilog Sources
reviewdog: Too many results (annotations) in diff.
You may miss some annotations due to GitHub limitation for annotation created by logging command.
Please check GitHub Actions log console to see all results.
Limitation:
- 10 warning annotations and 10 error annotations per step
- 50 annotations per job (sum of annotations from all the steps)
- 50 annotations per run (separate from the job annotations, these annotations aren't created by users)
Source: https://github.community/t5/GitHub-Actions/Maximum-number-of-annotations-that-can-be-created-using-GitHub/m-p/39085
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Verilog Sources
Process completed with exit code 1.
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Verilog Sources:
src/stream_omega_net.sv#L272
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:272 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L277
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 165 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 165 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:277 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L278
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:278 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L279
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:279 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L282
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 203 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 203 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:282 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L283
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 187 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 187 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:283 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L284
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:284 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L288
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:288 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L289
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:289 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verilog Sources:
src/stream_omega_net.sv#L290
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]" location:{path:"./src/stream_omega_net.sv" range:{start:{line:290 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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