CLIC v2.0.0

Added

• Design is now parametrizable through SystemVerilog without requiring an
  intermediate codegen step through python
• Kill handshake logic. Core and CLIC can now work together to allow higher
  level interrupts to overtake current interrupts that used to be stuck in a
  handshake.
• S-mode support

Changed

• Aligned to latest spec draft
• Memory map now follows the current clic draft (ie, ip, attr, ctrl)

Fixed

• Blocking assignments
• Missing signal declarations

CLIC v1.0.1

Fixed

• Fixed Bender.yml

CLIC v1.0.0

Added

• Initial version of RISC-V Core Local Interrupt Controller (CLIC)