Merge pull request #10 from pulp-platform/bluewww/misc-fixes

Various
pulp-platform · May 28, 2023 · f4bf3cd · f4bf3cd
2 parents 6217987 + 02cfeeb
commit f4bf3cd
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Showing 3 changed files with 10 additions and 10 deletions.
diff --git a/src/clic.sv b/src/clic.sv
@@ -271,7 +271,7 @@ module clic import mclic_reg_pkg::*; import clicint_reg_pkg::*; #(
   always_comb begin
     // Saturate nlbits if nlbits > clicintctlbits (nlbits > 0 && nlbits <= 8)
     mnlbits = INTCTLBITS;
-    if (mnlbits <= INTCTLBITS)
+    if (mclic_reg2hw.mcliccfg.mnlbits.q <= INTCTLBITS)
       mnlbits = mclic_reg2hw.mcliccfg.mnlbits.q;
   end
 

diff --git a/src/clicint_reg_top.sv b/src/clicint_reg_top.sv
@@ -116,7 +116,7 @@ module clicint_reg_top #(
   );
 
 
-  //   F[ie]: 7:7
+  //   F[ie]: 8:8
   prim_subreg #(
     .DW      (1),
     .SWACCESS("RW"),
@@ -266,7 +266,7 @@ module clicint_reg_top #(
   assign clicint_ip_wd = reg_wdata[0];
 
   assign clicint_ie_we = addr_hit[0] & reg_we & !reg_error;
-  assign clicint_ie_wd = reg_wdata[7];
+  assign clicint_ie_wd = reg_wdata[8];
 
   assign clicint_attr_shv_we = addr_hit[0] & reg_we & !reg_error;
   assign clicint_attr_shv_wd = reg_wdata[16];
@@ -286,7 +286,7 @@ module clicint_reg_top #(
     unique case (1'b1)
       addr_hit[0]: begin
         reg_rdata_next[0] = clicint_ip_qs;
-        reg_rdata_next[7] = clicint_ie_qs;
+        reg_rdata_next[8] = clicint_ie_qs;
         reg_rdata_next[16] = clicint_attr_shv_qs;
         reg_rdata_next[18:17] = clicint_attr_trig_qs;
         reg_rdata_next[23:22] = clicint_attr_mode_qs;

diff --git a/src/gen/clicint.hjson b/src/gen/clicint.hjson
@@ -21,20 +21,20 @@
   regwidth: "32",
   registers: [
     { name: "CLICINT",
-	    desc: "CLIC interrupt pending, enable, attribute and control",
-	    swaccess: "rw",
-	    hwaccess: "hro",
-	    fields: [
+      desc: "CLIC interrupt pending, enable, attribute and control",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
         { bits: "31:24", name: "CTL", desc: "interrupt control for interrupt" },
         { bits: "23:22", name: "ATTR_MODE", desc: "privilege mode of this interrupt", resval: 3},
         //{ bits: "21:19", name: "reserved" },
         { bits: "18:17", name: "ATTR_TRIG", desc: "specify trigger type for this interrupt" },
         { bits: "16", name: "ATTR_SHV", desc: "enable hardware vectoring for this interrupt" },
 
-        { bits: "7", name: "IE", desc: "interrupt enable for interrupt" },
+        { bits: "8", name: "IE", desc: "interrupt enable for interrupt" },
 
         { bits: "0", name: "IP", desc: "interrupt pending for interrupt", hwaccess: "hrw" },
-	    ],
+      ],
     }
   ]
 }