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[WIP] hw: Fix cluster narrow AxiID width
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@sermazz
sermazz committed Jan 30, 2025
1 parent 2584e65 commit b389d4c
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Showing 2 changed files with 16 additions and 13 deletions.
27 changes: 15 additions & 12 deletions hw/chimera_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,9 @@ module chimera_cluster
localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id);
localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id);

localparam int ClusterNarrowIdWidthIn = ClusterNarrowAxiMstIdWidth;
localparam int ClusterNarrowIdWidthOut = ClusterNarrowAxiMstIdWidth + 2;

typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t;
typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t;

Expand All @@ -72,8 +75,8 @@ module chimera_cluster
typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t;
typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t;

typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t;
typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t;
typedef logic [ClusterNarrowIdWidthIn-1:0] axi_cluster_slv_id_width_narrow_t;
typedef logic [ClusterNarrowIdWidthOut-1:0] axi_cluster_mst_id_width_narrow_t;

typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t;
typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t;
Expand All @@ -91,9 +94,9 @@ module chimera_cluster
`AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t,
axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t)

`AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t,
`AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t,
axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t)
`AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t,
`AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t,
axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t)

`AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t,
Expand Down Expand Up @@ -172,21 +175,21 @@ module chimera_cluster
AXI_BUS #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth )
) soc_to_cluster_axi_bus();
AXI_BUS_ASYNC_GRAY #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) async_soc_to_cluster_axi_bus();

axi_cdc_src_intf #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) soc_to_cluster_src_cdc_fifo_i (
Expand All @@ -203,21 +206,21 @@ module chimera_cluster
AXI_BUS #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth )
) cluster_to_soc_axi_bus();
AXI_BUS_ASYNC_GRAY #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) async_cluster_to_soc_axi_bus();

axi_cdc_dst_intf #(
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
.AXI_DATA_WIDTH ( ClusterDataWidth ),
.AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
.LOG_DEPTH ( 3 )
) cluster_to_soc_dst_cdc_fifo_i (
Expand Down Expand Up @@ -349,8 +352,8 @@ module chimera_cluster
.AXI_DATA_C2S_WIDTH ( ClusterDataWidth ),
.AXI_DMA_DATA_C2S_WIDTH ( WideDataWidth ),
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth),
.AXI_ID_IN_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_OUT_WIDTH ( ClusterNarrowAxiMstIdWidth ),
.AXI_ID_IN_WIDTH ( ClusterNarrowIdWidthIn ),
.AXI_ID_OUT_WIDTH ( ClusterNarrowIdWidthOut ),
.AXI_DMA_ID_OUT_WIDTH ( WideMasterIdWidth ),
.LOG_DEPTH ( 3 ),
.DATA_WIDTH ( 32 ), // ???
Expand Down
2 changes: 1 addition & 1 deletion hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ ExtClusters
64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000
};

localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;
localparam aw_bt ClusterNarrowAxiMstIdWidth = 2;

// Memory Island
localparam byte_bt MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;
Expand Down

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