ci: Move internal CI manifest to nonfree

.github/verible.waiver

@@ -1,9 +1,9 @@
-# Copyright 2022 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
 # Auto-generated configuration registers are waived
 waive --rule=typedef-structs-unions --location="hw/regs/*"
 waive --rule=line-length --location="hw/regs/*"
 waive --rule=no-trailing-spaces --location="hw/regs/*"
-waive --rule=parameter-name-style --location="hw/regs/*"
+waive --rule=parameter-name-style --location="hw/regs/*"

.github/workflows/gitlab-ci.yml

@@ -1,12 +1,21 @@
-# Copyright 2022 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
 # Author: Sergio Mazzola <[email protected]>
 
 name: gitlab-ci
 
-on: [ push, pull_request, workflow_dispatch ]
+on:
+  [ push, workflow_dispatch ]
+
+#on:
+#  push:
+#    branches:
+#      - main
+#      - devel
+#  pull_request:
+#  workflow_dispatch:
 
 jobs:
   gitlab-ci:

.github/workflows/lint.yml

@@ -1,12 +1,12 @@
-# Copyright 2022 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
 # Author: Sergio Mazzola <[email protected]>
 
 name: lint
 
-on: [ push, pull_request, workflow_dispatch ]
+on: [ push, workflow_dispatch ]
 
 jobs:
 
@@ -67,4 +67,4 @@ jobs:
           AllowShortLoopsOnASingleLine: true
           }
         exclude: |
-          ./sw/include/regs/*.h
+          ./sw/include/regs/*.h

.gitignore

@@ -30,4 +30,4 @@ modelsim.ini
 compile.tcl
 logs
 vsim.wlf
-*.transcript
+*.transcript

.gitlab-ci.yml

@@ -1,86 +1,25 @@
-# Copyright 2022 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
 # Author: Sergio Mazzola <[email protected]>
 
-variables:
-  # Enable colors in CI terminal
-  TERM: ansi
-  FORCE_COLOR: 1
-  # Toolchain
-  QUESTA_SEPP: questa-2022.3
-  VSIM: $QUESTA_SEPP vsim
-  RISCV_GCC_BINROOT: /usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin
-  CC: /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc
-  CXX: /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++
-  PYTHON: /usr/local/anaconda3-2022.05/bin/python3
-  CMAKE: cmake-3.28.3
-
-before_script:
-  # Set up environment
-  - export PATH=$RISCV_GCC_BINROOT:$PATH
-  - if [ -d .venv ]; then source .venv/bin/activate; fi
-  # Check environment variables
-  - env
+# We initialize the nonfree repo, then spawn a sub-pipeline from it
 
 stages:
-  - setup
-  - build
-  - test
-
-.base:
-  artifacts:
-    when: always
-    expire_in: 1 week
-
-setup-env:
-  extends: .base
-  stage: setup
-  script:
-    # Install python virtual environment
-    - $PYTHON -m venv .venv
-    - source .venv/bin/activate
-    - python3 -m pip install --upgrade pip
-    - python3 -m pip install -r requirements.txt
-  artifacts:
-    paths: [ ".venv" ]
-
-vsim-build:
-  extends: .base
-  stage: build
-  needs: [ setup-env ]
-  script:
-    # Checkout dependencies
-    - bender checkout
-    # Build hardware
-    - make chs-hw-init
-    - make snitch-hw-init
-    - make chs-sim-all
-    - make chim-sim
-    # Compile software
-    - make chim-sw
-    # Compile SoC in vsim
-    - cd target/sim/vsim
-    - $VSIM -c -do 'quit -code [source compile.tcl]'
-  dependencies:
-    - setup-env
-  artifacts:
-    paths: [ ".venv", "hw", "sw", "target/sim" ]
+  - nonfree
 
-vsim-test:
-  extends: .base
-  stage: test
-  needs: [ vsim-build ]
-  parallel:
-    matrix:
-      - TESTNAME: [testCluster, testClusterOffload]
-  script:
-    - cd target/sim/vsim
-    - $VSIM -c -l $TESTNAME.transcript -do "set BINARY ../../../sw/tests/$TESTNAME.memisl.elf; source start.chimera_soc.tcl; run -all"
-    - ../../../scripts/vsim_ret_error.sh $TESTNAME.transcript
-  dependencies:
-    - vsim-build
+init:
+  stage: nonfree
+  script: make chim-nonfree-init
   artifacts:
-    paths: [ ".venv", "hw", "sw", "target/sim", "$TESTNAME.transcript" ]
-    expire_in: 4 weeks
+    paths: [ nonfree/ci.yml ]
+
+subpipe:
+  stage: nonfree
+  needs: [ init ]
+  trigger:
+    include:
+      - artifact: nonfree/ci.yml
+        job: init
+    strategy: depend

chimera.mk

@@ -75,6 +75,19 @@ regenerate_soc_regs: $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/reg
 $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/regs/chimera_reg_top.sv: $(CHIM_ROOT)/hw/regs/chimera_regs.hjson
 	python $(CHIM_ROOT)/utils/reggen/regtool.py -r $< --outdir $(dir $@)
 
+
+# Nonfree components
+CHIM_NONFREE_REMOTE ?= [email protected]:pulp-restricted/chimera-nonfree.git
+CHIM_NONFREE_COMMIT ?= 48fafe39
+
+.PHONY: chim-nonfree-init
+chim-nonfree-init:
+	git clone $(CHIM_NONFREE_REMOTE) $(CHIM_ROOT)/nonfree
+	cd $(CHIM_ROOT)/nonfree && git checkout $(CHIM_NONFREE_COMMIT)
+
+-include $(CHIM_ROOT)/nonfree/nonfree.mk
+
+
 -include $(CHIM_ROOT)/bender.mk
 
 -include $(CHIM_ROOT)/sim.mk

scripts/vsim_ret_error.sh

@@ -1,10 +1,10 @@
 #!/usr/bin/env bash
 
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2024 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
-# Author: Sergio Mazzola, ETH Zurich
+# Author: Sergio Mazzola <[email protected]>
 
 # Parse the number of errors from the last occurrence in the transcript
 RET=$(grep -Po '(?<=Errors: )\d+' "$1" | tail -n 1)