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[FIXME] target/xilinx: Reduce genesys2 SoC clock to 48 MHz
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TheSmolBoi authored and paulsc96 committed Mar 6, 2024
1 parent c34f16a commit f6a32ef
Showing 1 changed file with 14 additions and 13 deletions.
27 changes: 14 additions & 13 deletions target/xilinx/scripts/impl_ip.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -28,25 +28,26 @@ switch $proj {
CONFIG.CLK_OUT2_PORT {clk_50} \
CONFIG.CLK_OUT3_PORT {clk_20} \
CONFIG.CLK_OUT4_PORT {clk_10} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {48.000} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \
CONFIG.MMCM_CLKFBOUT_MULT_F {6.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {12.000} \
CONFIG.MMCM_CLKIN1_PERIOD {5.000} \
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
CONFIG.MMCM_CLKOUT1_DIVIDE {20} \
CONFIG.MMCM_CLKOUT2_DIVIDE {50} \
CONFIG.MMCM_CLKOUT3_DIVIDE {100} \
CONFIG.MMCM_CLKOUT1_DIVIDE {25} \
CONFIG.MMCM_CLKOUT2_DIVIDE {60} \
CONFIG.MMCM_CLKOUT3_DIVIDE {120} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT1_JITTER {112.316} \
CONFIG.CLKOUT1_PHASE_ERROR {89.971} \
CONFIG.CLKOUT2_JITTER {129.198} \
CONFIG.CLKOUT2_PHASE_ERROR {89.971} \
CONFIG.CLKOUT3_JITTER {155.330} \
CONFIG.CLKOUT3_PHASE_ERROR {89.971} \
CONFIG.CLKOUT4_JITTER {178.053} \
CONFIG.CLKOUT4_PHASE_ERROR {89.971} \
CONFIG.CLKOUT1_JITTER {106.024} \
CONFIG.CLKOUT1_PHASE_ERROR {82.655} \
CONFIG.CLKOUT2_JITTER {122.473} \
CONFIG.CLKOUT2_PHASE_ERROR {82.655} \
CONFIG.CLKOUT3_JITTER {146.346} \
CONFIG.CLKOUT3_PHASE_ERROR {82.655} \
CONFIG.CLKOUT4_JITTER {167.577} \
CONFIG.CLKOUT4_PHASE_ERROR {82.655} \
] [get_ips $proj]
}
vcu128 {
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