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target/sim: Add VCS simulation flow (#163)
* vip: Various fixes for VCS, bump AXI * cheshire_pkg: Replace parameter by variables inside function * vcs: Add first version of vcs scripts * ci: Add vcs to CI * sim: Some cleanup * docs: Document simulation using VCS * Bender.yml: Update to newest AXI version * make: Use Bender flags variable for VCS compile script --------- Co-authored-by: Paul Scheffler <[email protected]>
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Original file line number | Diff line number | Diff line change |
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@@ -7,11 +7,13 @@ | |
# Paul Scheffler <[email protected]> | ||
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BENDER ?= bender | ||
VLOGAN ?= vlogan | ||
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# Caution: Questasim requires this to point to the *actual* compiler install path | ||
CXX_PATH := $(shell which $(CXX)) | ||
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VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps | ||
VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps | ||
VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps | ||
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# Common Bender flags for Cheshire RTL | ||
CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdcsclic_sv39 | ||
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@@ -61,7 +63,7 @@ chs-clean-deps: | |
###################### | ||
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CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git | ||
CHS_NONFREE_COMMIT ?= 99e58ec | ||
CHS_NONFREE_COMMIT ?= 99aa8d9 | ||
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CHS_PHONY += chs-nonfree-init | ||
chs-nonfree-init: | ||
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@@ -149,6 +151,10 @@ $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml | |
$(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS)" > $@ | ||
echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@ | ||
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$(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml | ||
$(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ | ||
chmod +x $@ | ||
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.PRECIOUS: $(CHS_ROOT)/target/sim/models | ||
$(CHS_ROOT)/target/sim/models: | ||
mkdir -p $@ | ||
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@@ -167,6 +173,7 @@ $(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/t | |
CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v | ||
CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v | ||
CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl | ||
CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh | ||
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########### | ||
# DRAMSys # | ||
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,57 @@ | ||
# #!/usr/bin/env bash | ||
# Copyright 2022 ETH Zurich and University of Bologna. | ||
# Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
# | ||
# Cyril Koenig <[email protected]> | ||
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TESTBENCH=tb_cheshire_soc | ||
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# Set full path to c++ compiler. | ||
if [ -z "${CXX_PATH}" ]; then | ||
if [ -z "${CXX}" ]; then | ||
CXX="g++" | ||
fi | ||
CXX_PATH=`which ${CXX}` | ||
fi | ||
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# Set default VCS binary | ||
[[ -z "${VERDI_VERSION}" ]] && VERDI_VERSION="" | ||
[[ -z "${VCS_VERSION}" ]] && VCS_VERSION="" | ||
[[ -z "${VCS_BIN}" ]] && VCS_BIN="${VCS_VERSION} vcs" | ||
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flags="-full64 -kdb " | ||
# Set default to fast simulation flags. | ||
if [ -z "${VCSARGS}" ]; then | ||
# Use -debug_access+all for waveform debugging | ||
flags+="-O2 -debug_access=r -debug_region=1,${TESTBENCH} " | ||
fi | ||
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flags+="-cpp ${CXX_PATH} " | ||
[[ -n "${SELCFG}" ]] && flags+="-pvalue+SelectedCfg=${SELCFG} " | ||
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pargs="" | ||
[[ -n "${BOOTMODE}" ]] && pargs+="+BOOTMODE=${BOOTMODE} " | ||
[[ -n "${PRELMODE}" ]] && pargs+="+PRELMODE=${PRELMODE} " | ||
[[ -n "${BINARY}" ]] && pargs+="+BINARY=${BINARY} " | ||
[[ -n "${IMAGE}" ]] && pargs+="+IMAGE=${IMAGE} " | ||
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# DRAMSys | ||
if [ -n "${USE_DRAMSYS}" ]; then | ||
flags+="-pvalue UseDramSys=${USE_DRAMSYS} " | ||
if [[ "${USE_DRAMSYS}" == 1 ]]; then | ||
DRAMSYS_ROOT="../dramsys" | ||
DRAMSYS_LIB="${DRAMSYS_ROOT}/build/lib" | ||
pargs+="+DRAMSYS_RES=${DRAMSYS_ROOT}/configs " | ||
pargs+="-sv_lib ${DRAMSYS_LIB}/libDRAMSys_Simulator " | ||
fi | ||
fi | ||
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COLOR_NC='\e[0m' | ||
COLOR_BLUE='\e[0;34m' | ||
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${VCS_BIN} ${flags} ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log | ||
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# Start simulation | ||
printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" | ||
${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs} | tee simulate.log |