target/xilinx: Fix CDC log depth, relax clock routing

pulp-platform · Feb 24, 2024 · d48cda6 · d48cda6
1 parent f9337b1
commit d48cda6
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Showing 3 changed files with 7 additions and 6 deletions.
diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
@@ -14,11 +14,11 @@
 # 200 MHz input clock
 set SYS_TCK 5
 create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p]
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -of [get_ports sys_clk_p]]
 
 # SoC clock is generated by clock wizard and its constraints
 set SOC_TCK 20.0
 set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]]
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets soc_clk]
 
 ############
 # Switches #
@@ -77,7 +77,8 @@ set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*]
 set_input_delay  -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
 set_input_delay  -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
 set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
-set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
+# TODO: fix this by raising it back up...
+set_output_delay -max -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
 
 #######
 # I2C #

diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc
@@ -14,11 +14,11 @@
 # 100 MHz input clock
 set SYS_TCK 10
 create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p]
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins i_bufds_sys_clk/O]
 
 # SoC clock is generated by clock wizard and its constraints
 set SOC_TCK 20.0
-set soc_clk {clk_50_clkwiz}
+set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]]
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets soc_clk]
 
 #######
 # MIG #

diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv
@@ -56,7 +56,7 @@ module dram_wrapper_xilinx #(
 `ifdef TARGET_VCU128
   localparam dram_cfg_t cfg = '{
     EnCdc         : 1,    // 333 MHz AXI (cf. CdcLogDepth)
-    CdcLogDepth   : 8,
+    CdcLogDepth   : 5,
     IdWidth       : 8,
     AddrWidth     : 32,
     DataWidth     : 512,
@@ -69,7 +69,7 @@ module dram_wrapper_xilinx #(
 `ifdef TARGET_GENESYS2
   localparam dram_cfg_t cfg = '{
     EnCdc         : 1,    // 200 MHz AXI (cf. CCdcLogDepth)
-    CdcLogDepth   : 8,
+    CdcLogDepth   : 5,
     IdWidth       : 4,    // Fixed
     AddrWidth     : 30,
     DataWidth     : 64,