target/xilinx: Fix Tcl lint on genesys2 constraints

pulp-platform · Jan 6, 2025 · bd51809 · bd51809
1 parent a282d86
commit bd51809
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
@@ -77,11 +77,15 @@ set_output_delay -max -clock $soc_clk [expr { $SOC_TCK * 0.35 }] [get_ports vga*
 # SPIM #
 ########
 
-set_input_delay -min -clock $soc_clk [expr { 0.10 * $SOC_TCK }] [get_ports {sd_d_* sd_cd_i spih_sd_*}]
-set_input_delay -max -clock $soc_clk [expr { 0.35 * $SOC_TCK }] [get_ports {sd_d_* sd_cd_i spih_sd_*}]
+set_input_delay -min -clock $soc_clk [expr { 0.10 * $SOC_TCK }] [ \
+    get_ports {sd_d_* sd_cd_i spih_sd_*}]
+set_input_delay -max -clock $soc_clk [expr { 0.35 * $SOC_TCK }] [ \
+    get_ports {sd_d_* sd_cd_i spih_sd_*}]
 # TODO: fix this by raising it back up...
-set_output_delay -min -clock $soc_clk [expr { 0.020 * $SOC_TCK }] [get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}]
-set_output_delay -max -clock $soc_clk [expr { 0.063 * $SOC_TCK }] [get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}]
+set_output_delay -min -clock $soc_clk [expr { 0.020 * $SOC_TCK }] [ \
+    get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}]
+set_output_delay -max -clock $soc_clk [expr { 0.063 * $SOC_TCK }] [ \
+    get_ports {sd_d_* sd_*_o spih_sd_* spih_csb_o}]
 
 #######
 # I2C #