Enable vCLIC

pulp-platform · Jan 24, 2025 · 6cc02a3 · 6cc02a3
1 parent fd1001b
commit 6cc02a3
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -494,7 +494,7 @@ package cheshire_pkg;
       CvxifEn               : 0,
       ZiCondExtEn           : 1,
       RVSCLIC               : cfg.Clic,
-      RVVCLIC               : 0,
+      RVVCLIC               : 1,
       RVF                   : 1,
       RVD                   : 1,
       FpPresent             : 1,
@@ -596,7 +596,7 @@ package cheshire_pkg;
     SerialLink        : 1,
     Vga               : 1,
     AxiRt             : 0,
-    Clic              : 0,
+    Clic              : 1,
     IrqRouter         : 0,
     BusErr            : 1,
     // Debug

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -676,9 +676,9 @@ module cheshire_soc import cheshire_pkg::*; #(
         .reg_rsp_t   ( reg_rsp_t ),
         .SSCLIC      ( 1 ),
         .USCLIC      ( 0 ),
-        .VSCLIC      ( 0 ),
-        .N_VSCTXTS   ( 0 ),
-        .VSPRIO      ( 0 ),
+        .VSCLIC      ( 1 ),
+        .N_VSCTXTS   ( 64 ),
+        .VSPRIO      ( 1 ),
         .VsprioWidth ( 1 )
       ) i_clic (
         .clk_i,

diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk
@@ -41,7 +41,7 @@ CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s
 CHS_XILINX_IPS_vcu128   := clkwiz vio ddr4
 
 $(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml
-	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@
+	$(BENDER) script vivado -t fpga -t cv64a6_imafdch_sv39_wb -t cva6 -t $* > $@
 
 define chs_xilinx_bit_rule
 $$(CHS_XILINX_DIR)/out/%.$(1).bit: \