axi_vga: Bump version to include an essential performance update

pulp-platform · Mar 14, 2024 · 3150aef · 3150aef
1 parent 3dca6cf
commit 3150aef
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Showing 4 changed files with 9 additions and 3 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -53,8 +53,8 @@ packages:
     - common_cells
     - register_interface
   axi_vga:
-    revision: 07be187d1e954d8090031b32d236ad76dc62ce45
-    version: 0.1.1
+    revision: ff82d9b85f68fedba091677c129d06c5a2720c20
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -17,7 +17,7 @@ dependencies:
   axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.2  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.4 }
-  axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }
+  axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                rev: perf-tbenz  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.32.0 }

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -161,6 +161,7 @@ package cheshire_pkg;
     byte_bt VgaBlueWidth;
     aw_bt   VgaHCountWidth;
     aw_bt   VgaVCountWidth;
+    dw_bt   VgaBufferDepth;
     // Parameters for Serial Link
     dw_bt   SlinkMaxTxnsPerId;
     dw_bt   SlinkMaxUniqIds;
@@ -621,6 +622,7 @@ package cheshire_pkg;
     VgaBlueWidth      : 2,
     VgaHCountWidth    : 24, // TODO: Default is 32; is this needed?
     VgaVCountWidth    : 24, // TODO: See above
+    VgaBufferDepth    : 16,
     // Serial Link: map other chip's lower 32bit to 'h1_000_0000
     SlinkMaxTxnsPerId : 4,
     SlinkMaxUniqIds   : 4,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -1589,9 +1589,13 @@ module cheshire_soc import cheshire_pkg::*; #(
       .VCountWidth  ( Cfg.VgaVCountWidth ),
       .AXIAddrWidth ( Cfg.AddrWidth    ),
       .AXIDataWidth ( Cfg.AxiDataWidth ),
+      .AXIIdWidth   ( Cfg.AxiMstIdWidth ),
+      .AXIUserWidth ( Cfg.AxiUserWidth ),
       .AXIStrbWidth ( AxiStrbWidth     ),
+      .BufferDepth  ( Cfg.VgaBufferDepth ),
       .axi_req_t    ( axi_mst_req_t ),
       .axi_resp_t   ( axi_mst_rsp_t ),
+      .axi_r_chan_t ( axi_mst_r_chan_t ),
       .reg_req_t    ( reg_req_t ),
       .reg_resp_t   ( reg_rsp_t )
     ) i_axi_vga (