treewide: Add bare-metal offload to safety island in carfield

* Standalone offload (JTAG/Serial Link)
* CVA6-driven offload
* Update README.md

.github/workflows/lint.yml

@@ -29,6 +29,7 @@ jobs:
           sw/include/regs/*.h
           .dir-locals.el
           utils/*
+          scripts/*
 
   lint-sv:
     runs-on: ubuntu-latest

.gitignore

@@ -12,6 +12,7 @@ work/
 /logs/
 /working_dir/
 
+sw/tests/bare-metal/safed/*.h
 
 # Created by https://www.toptal.com/developers/gitignore/api/python
 # Edit at https://www.toptal.com/developers/gitignore?templates=python

Bender.yml

@@ -32,6 +32,9 @@ workspace:
   package_links:
     cheshire: cheshire
     spatz: spatz
+    safety_island: safety_island
+    opentitan: opentitan
+    pulp_cluster: pulp_cluster
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -52,6 +55,7 @@ sources:
   - target: test
     files:
       - tb/hyp_vip/s27ks0641.v
+      - tb/vip_carfield_soc.sv
       - tb/carfield_fix.sv
       - tb/carfield_tb.sv
 
@@ -62,7 +66,7 @@ sources:
   - target: all(synthesis, not(fpga))
     files:
       - target/synth/carfield_synth_wrap.sv
-  
+
   - target: all(xilinx, fpga)
     files:
       - target/xilinx/src/carfield_top_xilinx.sv

README.md

@@ -18,28 +18,33 @@ To handle project dependencies, you can use
 
 ## Carfield Initialization
 To initialize Carfield, do the following:
- * Export the `RISCV` environment variable to the RISC-V toolchain. To work on IIS machines,
- do `export RISCV=/usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0`.
- * Execute the command:
+* Execute the command:
 
    ```
    make car-init
    ```
 
    It will take care of:
 
-   ** Clone all the Carfield dependencies;
-   ** Initialize the [Cheshire SoC](https://github.com/pulp-platform/cheshire). This can be
+   1. Clone all the Carfield dependencies;
+   2. Initialize the [Cheshire SoC](https://github.com/pulp-platform/cheshire). This can be
 	  done separately by running `make chs-init`
-   ** Downloads the Hyperram models from the iis-gitlab. If you don't have access to it, you
+   3. Downloads the Hyperram models from the iis-gitlab. If you don't have access to it, you
 	  can also download the freely-available Hyperram models from
 	  [here](https://www.cypress.com/documentation/models/verilog/s27kl0641-s27ks0641-verilog)
 	  and unzip them according to the bender.
 
+* Check that you have a RISCV toolchain for both RV64 and RV32 ISAs. For ETH, type:
+   ```
+   source scripts/env-iis.sh
+   ```
+
 ## Simulation
 
 Follow these steps to launch a Carfield simulation:
 
+### Compile HW and SW
+
 * Generate the compile scripts for Questasim and compile Carfield.
 
    ```
@@ -55,9 +60,11 @@ Follow these steps to launch a Carfield simulation:
   make car-sw-build
   ```
 
-* Simulate a binary in RTL. The current supported bootmodes from Cheshire are:
+### System bootmodes
+
+* The current supported bootmodes from Cheshire are:
 
-  | Bootmode | Preload mode | Action |
+  | `CHS_BOOTMODE` | `CHS_PRELMODE` | Action |
   | --- | --- | --- |
   | 0 | 0 | Passive bootmode, JTAG preload |
   | 0 | 1 | Passive bootmode, Serial Link preload |
@@ -66,18 +73,33 @@ Follow these steps to launch a Carfield simulation:
   | 2 | - | Autonomous bootmode, SPI flash |
   | 3 | - | Autonomous bootmode, I2C EEPROM |
 
-  `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode`
-  indicates the type of preload, if any is needed. For RTL simulation, bootmodes
-  0, 2 and 3 are supported. SPI SD card bootmode is supported on FPGA emulation.
+  `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode` indicates the type
+  of preload, if any is needed. For RTL simulation, bootmodes 0, 2 and 3 are supported. SPI SD card
+  bootmode is supported on FPGA emulation.
 
-  To launch an RTL simulation with the selected boot and preload modes, type:
+* The current supported bootmodes ffrom the Safety Island are:
 
-  | Bootmode | Command |
+  | `SAFED_BOOTMODE` | Action |
   | --- | --- |
-  | 0 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_BINARY=<chs_binary_path>.car.elf SECD_BINARY=<secd_binary_path> SAFED_BINARY=<safed_binary_path>`  |
-  | 1, 2, 3 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_IMAGE=<chs_binary_path>.car.memh`  |
+  | 0 | Passive bootmode, JTAG preload |
+  | 1 | Passive bootmode, Serial Link preload |
+
+### Simulation
+
+To launch an RTL simulation with the selected boot/preload modes for the island of choice, type:
+
+
+* For cheshire in passive bootmode (`CHS_BOOTMODE=0`), set `CHS_BINARY` for Cheshire
+
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_BINARY=<chs_binary_path>.car.elf PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
+
+* For cheshire in autonomous bootmode (`CHS_BOOTMODE` = {1,2,3}), set `CHS_IMAGE` for Cheshire
 
-  Default is passive bootmode with serial link preload.
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_IMAGE=<chs_binary_path>.car.memh PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
 
 ## License
 

bender-common.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

bender-safed.mk

@@ -0,0 +1,8 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Alessandro Ottaviano <[email protected]>
+
+# bender defines
+safed_defs += -D TARGET_SIMULATION

bender-synth.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

carfield.mk

@@ -14,14 +14,12 @@ CAR_SW_DIR := $(CAR_ROOT)/sw
 CAR_XIL_DIR := $(CAR_ROOT)/target/xilinx
 CAR_HW_DIR := $(CAR_ROOT)/hw
 
-# Bender
 BENDER   ?= bender
 QUESTA   ?= questa-2022.3
 VIVADO   ?= vitis-2020.2 vivado
 TBENCH   ?= tb_carfield_soc
-BOOTMODE ?= 0 # default passive bootmode
-PRELMODE ?= 1 # default serial link preload
 VOPTARGS ?=
+
 # Interrupt configuration in cheshire
 # CLINT interruptible harts
 CLINTCORES     := 3
@@ -30,26 +28,47 @@ PLICCORES      := 6
 # PLIC number of input interrupts
 PLIC_NUM_INTRS := 89
 
+# Cheshire
+CHS_ROOT ?= $(shell $(BENDER) path cheshire)
 # Include cheshire's makefrag only if the dependency was cloned
 -include $(CHS_ROOT)/cheshire.mk
 
-# Spatz
-SPATZ_ROOT ?= $(CAR_ROOT)/spatz
-SPATZ_MAKEDIR := $(SPATZ_ROOT)/hw/system/spatz_cluster
-
-TESTNAME ?= helloworld
-MEMTYPE  ?= spm
-CHS_BINARY   ?= $(CAR_ROOT)/sw/tests/hostd/$(TESTNAME).car.$(MEMTYPE).elf
-SECD_BINARY  ?= # TODO: secd sw root
-SAFED_BINARY ?= # TODo: safed sw root
+CHS_BOOTMODE ?= 0 # default passive bootmode
+CHS_PRELMODE ?= 1 # default serial link preload
+CHS_BINARY   ?= 
 CHS_IMAGE    ?=
 
+# Safety Island
+SAFED_ROOT     ?= $(shell $(BENDER) path safety_island)
+SAFED_SW_DIR   := $(SAFED_ROOT)/sw
+SAFED_BOOTMODE ?= 0
+SAFED_BINARY   ?=
+
+# Security island
+SECD_ROOT     ?= $(shell $(BENDER) path opentitan)
+SECD_BINARY   ?=
+SECD_BOOTMODE ?=
+
+# PULP cluster
+PULPCL_ROOT   ?= $(shell $(BENDER) path pulp_cluster)
+PULPCL_BINARY ?=
+
+# Spatz cluster
+SPATZCL_ROOT    ?= $(shell $(BENDER) path spatz)
+SPATZCL_MAKEDIR := $(SPATZCL_ROOT)/hw/system/spatz_cluster
+SPATZCL_BINARY  ?=
+
+# Default variable values for RTL simulation
+TBENCH         ?= tb_carfield_soc
+OPTARGS        ?=
+
 # Include bender targets and defines for common usage and synth verification
 # (the following includes are mandatory)
 include $(CAR_ROOT)/bender-common.mk
 include $(CAR_ROOT)/bender-sim.mk
 include $(CAR_ROOT)/bender-synth.mk
 include $(CAR_ROOT)/bender-xilinx.mk
+include $(CAR_ROOT)/bender-safed.mk
 
 # Setup Virtual Environment for python scripts (reggen)
 VENVDIR?=$(WORKDIR)/.venv
@@ -69,7 +88,7 @@ endif
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= f09457c9aabc3b150ae36c854961e89b679360aa
+CAR_NONFREE_COMMIT ?= 72bdf4836596be7c3a939e6bea71924811066e86
 
 ## Clone the non-free verification IP for the Carfield TB
 car-nonfree-init:
@@ -88,16 +107,16 @@ include $(CAR_SW_DIR)/sw.mk
 ##############
 # Simulation #
 ##############
-.PHONY: hw/regs/carfield_regs.hjson
-hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
+.PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson
+$(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
 	$(VENV)/python ./scripts/csv_to_json.py --input $< --output $@
 
-.PHONY: hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
-hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv: hw/regs/carfield_regs.hjson | venv
+.PHONY: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
+$(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
 	$(VENV)/python utils/reggen/regtool.py -r $< --outdir $(dir $@)
 
-.PHONY: sw/include/regs/soc_ctrl.h
-sw/include/regs/soc_ctrl.h: hw/regs/carfield_regs.hjson | venv
+.PHONY: $(CAR_SW_DIR)/include/regs/soc_ctrl.h
+$(CAR_SW_DIR)/include/regs/soc_ctrl.h: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
 	$(VENV)/python utils/reggen/regtool.py -D $<  > $@
 
 ## @section Carfield SoC HW Generation
@@ -106,7 +125,7 @@ sw/include/regs/soc_ctrl.h: hw/regs/carfield_regs.hjson | venv
 ## hw/regs/carfield_regs.csv. You don't have to run this target unless you changed the CSV file. The
 ## checked-in pregenerated register file RTL should be up-to-date. If you regenerate the regfile, do
 ## not forget to check in the generated RTL.
-regenerate_soc_regs: hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
+regenerate_soc_regs: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv $(CAR_SW_DIR)/include/regs/soc_ctrl.h 
 
 ## @section Carfield CLINT and PLIC interruptible harts configuration
 
@@ -134,7 +153,7 @@ $(CAR_ROOT)/tb/hyp_vip:
 
 .PHONY: scripts/carfield_compile.tcl
 scripts/carfield_compile.tcl:
-	$(BENDER) script vsim $(common_targs) $(sim_targs) $(common_defs) --vlog-arg="$(VLOG_ARGS)" --compilation-mode separate > $@
+	$(BENDER) script vsim $(common_targs) $(sim_targs) $(common_defs) $(safed_defs) --vlog-arg="$(VLOG_ARGS)" --compilation-mode separate > $@
 	echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
 
 .PHONY: car-sim-init
@@ -155,7 +174,21 @@ car-hw-build: car-sim-init
 ## @param VOPTARGS="" Additional arguments to Questa's vopt command.
 ## @param TBENCH=tb_carfield_soc The toplevel testbench to use. Defaults to 'tb_carfield_soc'.
 car-hw-sim:
-	$(QUESTA) vsim $(VSIM_FLAG) -do "set BOOTMODE $(BOOTMODE); set PRELMODE $(PRELMODE); set CHS_BINARY $(CHS_BINARY); set SECD_BINARY $(SECD_BINARY); set SAFED_BINARY $(SAFED_BINARY); set VOPTARGS $(VOPTARGS); set CHS_IMAGE $(CHS_IMAGE); set TESTBENCH $(TBENCH); source scripts/start_carfield.tcl ; add log -r sim:/$(TBENCH)/*; $(RUN_AND_EXIT)"
+	$(QUESTA) vsim $(VSIM_FLAG) -do \
+		"set CHS_BOOTMODE $(CHS_BOOTMODE); \
+		 set CHS_PRELMODE $(CHS_PRELMODE); \
+		 set CHS_BINARY $(CHS_BINARY); \
+		 set CHS_IMAGE $(CHS_IMAGE); \
+		 set SECD_BINARY $(SECD_BINARY); \
+		 set SAFED_BOOTMODE $(SAFED_BOOTMODE); \
+		 set SAFED_BINARY $(SAFED_BINARY); \
+		 set PULPCL_BINARY $(PULPCL_BINARY); \
+		 set SPATZCL_BINARY $(SPATZCL_BINARY); \
+		 set VOPTARGS $(VOPTARGS); \
+		 set TESTBENCH $(TBENCH); \
+		 source scripts/start_carfield.tcl ; \
+		 add log -r sim:/$(TBENCH)/*; \
+		 $(RUN_AND_EXIT)"
 
 .PHONY: car-hw-clean
 ## Remove all simulation build artifacts
@@ -193,7 +226,7 @@ car-hw-init: spatz-hw-init chs-hw-init
 
 .PHONY: spatz-hw-init
 spatz-hw-init:
-	$(MAKE) -C $(SPATZ_MAKEDIR) -B SPATZ_CLUSTER_CFG=$(CAR_HW_DIR)/cfg/spatz_carfield.hjson bootrom
+	$(MAKE) -C $(SPATZCL_MAKEDIR) -B SPATZ_CLUSTER_CFG=$(CAR_HW_DIR)/cfg/spatz_carfield.hjson bootrom
 
 .PHONY: chs-hw-init
 ## This target has a prerequisite, i.e. the PLIC configuration must be chosen before generating the
@@ -209,17 +242,28 @@ chs-sim-init:
 .PHONY: chs-sw-build
 ## Builds the SW libraries in cheshire and generates an archive (`libcheshire.a`) available for
 ## carfield as static library at link time.
-chs-sw-build:
-	$(MAKE) chs-sw-all
+chs-sw-build: chs-sw-all
 
 .PHONY: car-sw-build
 ## Builds carfield application SW and specific libraries. It links against `libcheshire.a`.
-car-sw-build: chs-sw-build
-	$(MAKE) car-sw-all
+car-sw-build: chs-sw-build car-sw-all
 
 .PHONY: car-init
 ## Shortcut to initialize carfield with all the targets described above.
-car-init: car-checkout car-hw-init car-sim-init car-sw-build
+car-init: car-checkout car-hw-init car-sim-init safed-sw-init
+
+# Initialize and build Safety Island SW
+.PHONY: safed-sw-init
+safed-sw-init: $(SAFED_ROOT) $(SAFED_SW_DIR)/pulp-runtime $(SAFED_SW_DIR)/pulp-freertos
+
+$(SAFED_SW_DIR)/pulp-runtime: $(SAFED_ROOT)
+	$(MAKE) -C $(SAFED_ROOT) pulp-runtime
+$(SAFED_SW_DIR)/pulp-freertos: $(SAFED_ROOT)
+	$(MAKE) -C $(SAFED_ROOT) pulp-freertos
+
+# For independent boot of an island, we allow to compile the binary standalone.
+.PHONY: safed-sw-build
+safed-sw-build: safed-sw-init safed-sw-all
 
 ############
 # RTL LINT #

hw/carfield.sv

@@ -288,10 +288,10 @@ logic [CheshireNumIntHarts-1:0] safed_hostd_mbox_intr;   // from safety island t
 localparam axi_in_t   AxiIn   = gen_axi_in(Cfg);
 localparam axi_out_t  AxiOut  = gen_axi_out(Cfg);
 
-/*****************************/
-/* Wide Parameters: A48, D32 */
-/*****************************/
-localparam int unsigned AxiStrbWidth  = Cfg.AxiDataWidth / 8;
+///////////////////////////////
+// Wide Parameters: A48, D32 //
+///////////////////////////////
+
 localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in);
 
 // Wide AXI types

hw/carfield_pkg.sv

@@ -374,9 +374,7 @@ localparam doub_bt L2Port2NonInterlBase = L2Port2Base + L2MemSize;
 /****************************/
 localparam int unsigned LogDepth = 3;
 localparam int unsigned SafetyIslandMemOffset = 'h0000_0000;
-localparam int unsigned SafetyIslandMemSize   = 'h0020_0000;
 localparam int unsigned SafetyIslandPerOffset = 'h0020_0000;
-localparam int unsigned SafetyIslandPerSize   = 'h0010_0000;
 
 /******************************/
 /* Integer Cluster Parameters */

requirements.txt

@@ -2,3 +2,4 @@ hjson==3.1.0
 Mako==1.1.6
 PyYAML==6.0
 pandas==1.0.1
+pyelftools==0.29