Add support for VCU118 block design (#287)

* fpga: Testing hyperram in block design * fpga: Testing hyperram in vanilla * fpga: Correct Xilinx IP verilog to follow the standard * fpga: Adding hyperram CDC constraints * fpga: Adding pads in vanilla * fpga: Adding vcu118 BD support * fpga: Cleaning PR * vcu118: Ethernet debug * docs: Updated Xilinx targets * fpga: Removed hyperbus for this PR * fpga: CI and flash script * fpga: Debug once again spi * fpga: Changing STARTUPE3 tie-off * fpga: Reset board after program * sw: New dts for vcu118 * ci: Update for FPGA * misc: Update docs and licenses
pulp-platform · Jan 24, 2025 · 7908f99 · 7908f99
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diff --git a/carfield.mk b/carfield.mk
@@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= 59e53134
+CAR_NONFREE_COMMIT ?= e39aebd1
 
 ## @section Carfield platform nonfree components
 ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC

diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md
@@ -8,7 +8,12 @@ Additionally, for on-chip debugging you need:
 
 We currently provide working setups for:
 
-- Xilinx VCU128 with Vivado `>= 2020.2`
+- Xilinx VCU128 with Vivado `== 2020.2`
+- Xilinx VCU118 with Vivado `== 2020.2`
+
+:warning: At the moment it is required to use the Vivado version above
+
+**Note: Certain version of Vivado might cause issue, until these issues are resolved it is safer to use 2020.2**
 
 We are working on support for more boards in the future.
 
@@ -24,7 +29,17 @@ design flow to link Carfield with external IPs. This flow is less human readable
 integrating more complex IPs as Xilinx Ethernet. *Note that this may require you to own the
 respective licenses.*
 
-## Building the vanilla bistream
+## Quick Start
+
+The recommended command to build a bitstream (for VCU128) is
+
+```bash
+make car-xil-all XILINX_FLAVOR=bd VIVADO="vitis-2020.2 vivado" VIVADO_MODE=gui XILINX_BOARD=vcu128 GEN_NO_HYPERBUS=1 GEN_EXT_JTAG=1 CARFIELD_CONFIG=carfield_l2dual_spatz_periph
+```
+
+Please find below more explanations.
+
+## Building the vanilla bistream (VCU128 only)
 
 Due to the structure of the Makefile flow. All the following commands are to be executed at the root
 of the Carfield repository. If you want to see the Makefiles that you will be using, you can find
@@ -90,7 +105,7 @@ Generate the bitstream in `target/xilinx/out/` by running:
 
 ```bash
 make car-xil-all XILINX_FLAVOR=bd [VIVADO=version] [VIVADO_MODE={batch,gui}]
-[XILINX_BOARD={vcu128}] [GEN_NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}]
+[XILINX_BOARD={vcu128, vcu118}] [GEN_NO_HYPERBUS={0,1}] [GEN_EXT_JTAG={0,1}]
 [CARFIELD_CONFIG=carfield_l2dual_{safe,spatz}_periph]
 ```
 
@@ -99,12 +114,12 @@ See the argument list below:
 | Argument        | Relevance | Description                                                                                                                           |
 |---------------- |-----------|---------------------------------------------------------------------------------------------------------------------------------------|
 | VIVADO          | all       | Vivado command to use                                                                                                                 |
-| XILINX_BOARD    | all       | `vcu128`                                                                                                                              |
+| XILINX_BOARD    | all       | `vcu128` `vcu118`                                                                                                                              |
 | GEN_NO_HYPERBUS | all       | `0` Use the hyperram controller inside `carfield.sv`<br>`1` Use the Xilinx DDR controller                                             |
-| GEN_EXT_JTAG    | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
+| GEN_EXT_JTAG    | all    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
 | CARFIELD_CONFIG | all       | Select the Carfield configuration to implement. See below for supported configs.                                                      |
 | VIVADO_MODE     | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
-| XILINX_BOOT_ETH | all       | `0` Boot via SPI flash only (see [booting Linux](#booting_linux)) <br>`1` Boot via SPI flash and Ethernet                             |
+| XILINX_BOOT_ETH | vcu128       | `0` Boot via SPI flash only (see [booting Linux](#booting_linux)) <br>`1` Boot via SPI flash and Ethernet                             |
 
 See below some typical building time for reference:
 
@@ -141,19 +156,34 @@ can be set in the Vivado GUI (see [Using Vivado GUI](#bringup_vivado_gui)).
 > The VCU128 development board only provides one JTAG chain, used by Vivado to program the
 bitstream, and interact with certain Xilinx IPs (ILAs, VIOs, ...). The RV64 requires access to a
 JTAG chain to connect GDB to the debug-module in the bitstream.
-
 > When using `EXT_JTAG=0` it is possible to connect the debug module to the internal FPGA's JTAG by
 using the Xilinx BSCANE macro. With this, you will only need the normal Xilinx USB cable to interact
 with CVA6. Note that it means that
 Vivado and OpenOCD can not use the same cable at the same time.
->**WARNING: this setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as
+> :warning: This setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as
 it is not possible to chain multiple devices on the BSCANE macro. If you need to use `EXT_JTAG=0`
 consider modifying the RTL to remove the debug modules of the IPs.
-
 > When using `EXT_JTAG=1` we add an external JTAG chain for the RV64 host and other island through
 the FPGA's GPIOs. Since the VCU128 does not have GPIOs we use we use a Digilent JTAG-HS2 cable
 connected to the Xilinx XM105 FMC debug card. See the connections in `vcu128.xdc`.
 
+### Xilinx VCU118
+> #### Bootmodes and VIOs
+>
+> We currently do not use the switches on this board, the CVA6 bootmode (see [Cheshire
+bootrom](https://pulp-platform.github.io/cheshire/um/sw/#boot-rom)) is selected by Xilinx VIOs that
+can be set in the Vivado GUI (see [Using Vivado GUI](#bringup_vivado_gui)).
+>
+> #### External JTAG chain
+>
+> Similarly to the VCU128 we use GPIOs to connect an external JTAG-USB dongle (Digilent HS2). Unlike the VCU128, the availability of GPIOs directly on the board allow us to connect the HS2 without an FMC debug board (see constraints for related pins).
+>**WARNING: this setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as
+it is not possible to chain multiple devices on the BSCANE macro. If you need to use `EXT_JTAG=0`
+consider modifying the RTL to remove the debug modules of the IPs.
+> #### Block design and Xilinx Ethernet IP
+>
+> The Xilinx Ethernet IP integration is still under debug and does not work out of the box in Linux or U-boot at the moment.
+
 ## Bare-metal bringup
 
 ### Programming the FPGA
@@ -248,7 +278,7 @@ integrated flash:
 > This script will erase your bitstream, once the flash has been written (c.a.
 10min) you will need to re-program the bitstream on the board.
 > You can attach the UART port of the FPGA to minicom and see the boot process! 
-### Via Ethernet
+### Via Ethernet (VCU128 only)
 >
 > As flashing and reading the kernel from SPI can take a few minutes, a faster way is to
 > [ask U-Boot to fetch the image from the network](https://www.emcraft.com/som/using-dhcp).
@@ -259,9 +289,6 @@ integrated flash:
 > ```
 > make chs-xil-flash VIVADO_MODE=batch XILINX_BOARD=vcu128 XILINX_FLAVOR=bd XILINX_BOOT_ETH=1
 > ```
-### Via Ethernet
-
-Tbd
 
 ## Add your own board
 

diff --git a/sw/boot/carfield_bd_vcu118.dts b/sw/boot/carfield_bd_vcu118.dts
@@ -0,0 +1,8 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+
+/include/ "carfield.dtsi"
diff --git a/sw/boot/remote_boot.dtsi b/sw/boot/remote_boot.dtsi
@@ -1,2 +1,2 @@
 // Uncomment below for remote boot
-// remote-boot = "0.0.0.0:vcu128-01/carfield/uImage-ci";
+// remote-boot = "0.0.0.0:vcu128-01/carfield/uImage-ci";
diff --git a/target/xilinx/constraints/carfield_islands.tcl b/target/xilinx/constraints/carfield_islands.tcl
@@ -41,13 +41,31 @@ handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk
 # Carfield CDCs #
 #################
 
-# Safety Island
-################
+## Find the first parent cell of matching module from a list of object paths
+## @param strs children objects paths
+## @param ref_to_find the module type of the parent cell
+proc find_parent_cell { strs ref_to_find } {
+  foreach str $strs {
+    set path ".";
+    foreach cell [split $str '/'] {
+      if {[get_cells -quiet $path] != ""} {
+        if { [get_property "ORIG_REF_NAME" [get_cell $path]] == $ref_to_find } {
+          return $path
+        }
+        if { [get_property "REF_NAME" [get_cell $path]] == $ref_to_find } {
+          return $path
+        }
+      }
+      set path $path/$cell;
+    }
+  }
+  return ""
+}
 
 proc handle_slv_cdc { slv_cdc_path } {
   upvar SOC_TCK SOC_TCK
   # Start from a known slv cdc_dst and get fanout to find the mst cdc_src
-  set mst_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_slv_cdc_src|.*i_intcluster_slv_cdc} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
+  set mst_cdc_path [find_parent_cell [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] "axi_cdc_src"]
   if { $mst_cdc_path != "" } {
     set_max_delay -datapath \
      -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
@@ -66,7 +84,6 @@ proc handle_slv_cdc { slv_cdc_path } {
      -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
      "$SOC_TCK"
   }
-
 }
 
 handle_slv_cdc [get_cells -hier gen_periph.i_cdc_dst_peripherals]
@@ -76,12 +93,12 @@ handle_slv_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_in
 handle_slv_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_dst
 handle_slv_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_slave_cdc_i
 handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_dst_cdc
+handle_slv_cdc [get_cells -hier i_hyperbus_wrap]/i_hyper_cdc_dst
 
 proc handle_mst_cdc { mst_cdc_path } {
   upvar SOC_TCK SOC_TCK
-  # Get the dst_cdc in cheshire
-  set slv_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_mst_cdc_dst|.*i_intcluster_mst_cdc} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
-
+  # Start from a known mst cdc_src and get fanout to find the slv cdc_dst
+  set slv_cdc_path [find_parent_cell [all_fanout -flat [get_pins $mst_cdc_path/*rptr*]] "axi_cdc_dst"]
   if { $slv_cdc_path != "" } {
     # From Safety Island master
     set_max_delay -datapath \
@@ -101,7 +118,6 @@ proc handle_mst_cdc { mst_cdc_path } {
      -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
      "$SOC_TCK"
   }
-
 }
 
 handle_mst_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_out

diff --git a/target/xilinx/flavor_bd/.gitignore b/target/xilinx/flavor_bd/.gitignore
@@ -1,6 +1,9 @@
-.Xil
-carfield_*
-scripts/add_sources.tcl*
-scripts/add_includes.tcl
-out/
-probes.ltx
+# Makefile
+/out/
+# Bender
+/scripts/add_sources.tcl*
+/scripts/add_includes.tcl
+# Vivado
+/.Xil
+/carfield_*
+/probes.ltx
diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc
@@ -0,0 +1,40 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
+# VIOs are asynchronous
+set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
+
+# Create system clocks
+create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+
+# PCIe clock LOC
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]]
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]]
+
+set_property PACKAGE_PIN AW25     [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
+set_property PACKAGE_PIN BB21     [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
+#set_property PACKAGE_PIN BB22     [get_ports "uart_rts_o"] ;
+#set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rts_o"] ;
+#set_property PACKAGE_PIN AY25     [get_ports "uart_cts_i"] ;
+#set_property IOSTANDARD  LVCMOS18 [get_ports "uart_cts_i"] ;
+
+set_property PACKAGE_PIN L19      [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
+set_property IOSTANDARD  LVCMOS12 [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
+
+set_property BOARD_PART_PIN default_250mhz_clk1_n [get_ports default_250mhz_clk1_clk_n]
+set_property BOARD_PART_PIN default_250mhz_clk1_p [get_ports default_250mhz_clk1_clk_p]
+
+set_property PACKAGE_PIN D12      [get_ports default_250mhz_clk1_clk_n]    ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_n] ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
+set_property PACKAGE_PIN E12      [get_ports default_250mhz_clk1_clk_p]    ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank  71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc
@@ -0,0 +1,17 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+#
+set_property PACKAGE_PIN N30     [get_ports jtag_tdo_o]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o]
+
+set_property PACKAGE_PIN P30     [get_ports jtag_tck_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i]
+
+set_property PACKAGE_PIN N28     [get_ports jtag_tms_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i]
+
+set_property PACKAGE_PIN M30     [get_ports jtag_tdi_i]
+set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i]
diff --git a/target/xilinx/flavor_bd/constraints/vcu128.xdc b/target/xilinx/flavor_bd/constraints/vcu128.xdc
@@ -1,3 +1,9 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
 # VIOs are asynchronous
 set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
 

diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc
@@ -1,3 +1,9 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
 set_property PACKAGE_PIN A23     [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND
 set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ;