Optionally enable zfinx and 32b floating point architecture

pulp-platform · Jan 28, 2025 · edd0675 · edd0675
1 parent 9153635
commit edd0675
Show file tree

Hide file tree

Showing 5 changed files with 400 additions and 131 deletions.
diff --git a/config/mempool.yaml b/config/mempool.yaml
@@ -40,6 +40,9 @@ memory:
         size: 0x10000
       - name: mempool-dma
         size: 0x1C
+float_instr:
+  width: 32
+  zfinx: true
 inst_latency:
   mul: 3
   mulh: 3

diff --git a/config/terapool.yaml b/config/terapool.yaml
@@ -40,6 +40,9 @@ memory:
         size: 0x10000
       - name: mempool-dma
         size: 0x1C
+float_instr:
+  width: 32
+  zfinx: true
 inst_latency:
   mul: 4
   mulh: 4

diff --git a/src/configuration.rs b/src/configuration.rs
@@ -21,6 +21,8 @@ pub struct Configuration {
     #[serde(default)]
     pub address: Address,
     #[serde(default)]
+    pub float_instr: FloatInstr,
+    #[serde(default)]
     pub inst_latency: std::collections::HashMap<String, u64>,
     #[serde(default)]
     pub ssr: Ssr,
@@ -35,6 +37,7 @@ impl Default for Configuration {
             bootrom: Default::default(),
             memory: Default::default(),
             address: Default::default(),
+            float_instr: Default::default(),
             inst_latency: Default::default(),
             ssr: Default::default(),
             interrupt_latency: 10,
@@ -56,6 +59,7 @@ impl Configuration {
             memory: Default::default(),
             address: Default::default(),
             inst_latency: Default::default(),
+            float_instr: Default::default(),
             ssr: Default::default(),
             interrupt_latency: 10,
         }
@@ -246,6 +250,21 @@ impl Default for Ssr {
     }
 }
 
+/// Struct to configure the floating-point ISA features
+#[derive(Debug, serde::Serialize, serde::Deserialize)]
+pub struct FloatInstr {
+    pub width: usize,
+    pub zfinx: bool,
+}
+
+impl Default for FloatInstr {
+    fn default() -> FloatInstr {
+        FloatInstr {
+            width: 32,
+            zfinx: false }
+    }
+}
+
 /// Description of the hierarchy
 #[derive(Debug, serde::Serialize, serde::Deserialize, Clone)]
 pub struct Architecture {

diff --git a/src/engine.rs b/src/engine.rs
@@ -1185,18 +1185,31 @@ impl<'a, 'b> Cpu<'a, 'b> {
         // Assemble the arguments.
         let args = accesses.iter().copied().zip(data.iter().copied());
         let mut args = args.map(|(access, data)| match access {
+            // Memory access cases
             TraceAccess::ReadMem(_x) => format!("RA:{:08x}", data as u32),
             TraceAccess::WriteMem => format!("WA:{:08x}", data as u32),
             TraceAccess::RMWMem => format!("AMO:{:08x}", data as u32),
+
+            // Register access cases
             TraceAccess::ReadReg(x) => format!("x{}:{:08x}", x, data as u32),
             TraceAccess::WriteReg(x) => format!("x{}={:08x}", x, data as u32),
-            TraceAccess::ReadFReg(x) => format!("f{:02}:{:>16.6}", x, f64::from_bits(data)),
-            TraceAccess::WriteFReg(x) => format!("f{:02}={:>16.6}", x, f64::from_bits(data)),
-            TraceAccess::ReadF32Reg(x) => {
-                format!("f{:02}:{:>12.4}", x, f32::from_bits(data as u32))
-            }
-            TraceAccess::WriteF32Reg(x) => {
-                format!("f{:02}={:>12.4}", x, f32::from_bits(data as u32))
+
+            // Floating-point register access cases
+            TraceAccess::ReadFReg(x)
+            | TraceAccess::WriteFReg(x)
+            | TraceAccess::ReadF32Reg(x)
+            | TraceAccess::WriteF32Reg(x) => {
+                if self.engine.config.float_instr.zfinx {
+                    format!("x{}={:08x}", x, data as u32)
+                } else {
+                    match access {
+                        TraceAccess::ReadFReg(_) => format!("f{:02}:{:>16.6}", x, f64::from_bits(data)),
+                        TraceAccess::WriteFReg(_) => format!("f{:02}={:>16.6}", x, f64::from_bits(data)),
+                        TraceAccess::ReadF32Reg(_) => format!("f{:02}:{:>12.4}", x, f32::from_bits(data as u32)),
+                        TraceAccess::WriteF32Reg(_) => format!("f{:02}={:>12.4}", x, f32::from_bits(data as u32)),
+                        _ => unreachable!(),
+                    }
+                }
             }
             TraceAccess::Readf8Reg(x) => format!(
                 "f{:02}:[{:>5.3}]",
@@ -1218,26 +1231,36 @@ impl<'a, 'b> Cpu<'a, 'b> {
                     false
                 ) as u32),
             ),
-            TraceAccess::Readf16Reg(x) => format!(
-                "f{:02}=[{:>8.4}]",
-                x,
-                f32::from_bits(flexfloat::ff_instruction_cvt_to_s(
-                    (data & 0x0000_0000_0000_ffff) >> 0,
-                    flexfloat::FfOpCvt::Fcvt16f2f,
-                    false,
-                    false
-                ) as u32),
-            ),
-            TraceAccess::Writef16Reg(x) => format!(
-                "f{:02}=[{:>5.3}]",
-                x,
-                f32::from_bits(flexfloat::ff_instruction_cvt_to_s(
-                    (data & 0x0000_0000_0000_00ff) >> 0,
-                    flexfloat::FfOpCvt::Fcvt16f2f,
-                    false,
-                    false
-                ) as u32),
-            ),
+            TraceAccess::Readf16Reg(x) =>
+                if self.engine.config.float_instr.zfinx {
+                    format!("x{}={:08x}", x, data as u32)
+                } else {
+                    format!(
+                        "f{:02}=[{:>8.4}]",
+                        x,
+                        f32::from_bits(flexfloat::ff_instruction_cvt_to_s(
+                            (data & 0x0000_0000_0000_ffff) >> 0,
+                            flexfloat::FfOpCvt::Fcvt16f2f,
+                            false,
+                            false
+                        ) as u32),
+                    )
+                },
+            TraceAccess::Writef16Reg(x) =>
+            if self.engine.config.float_instr.zfinx {
+                format!(
+                    "f{:02}=[{:>5.3}]",
+                    x,
+                    f32::from_bits(flexfloat::ff_instruction_cvt_to_s(
+                        (data & 0x0000_0000_0000_00ff) >> 0,
+                        flexfloat::FfOpCvt::Fcvt16f2f,
+                        false,
+                        false
+                    ) as u32),
+                )
+            } else {
+                format!("x{}={:08x}", x, data as u32)
+            },
             TraceAccess::Readvf64sReg(x) => format!(
                 "f{:02}:[{:>12.4}, {:>12.4}]",
                 x,