Default FULL_BANDWIDTH at 1 to not break back compatibility.

pulp-platform · May 8, 2024 · 571299c · 571299c
1 parent 6a85f44
commit 571299c
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Showing 5 changed files with 5 additions and 5 deletions.
diff --git a/src/axi_riscv_atomics.sv b/src/axi_riscv_atomics.sv
@@ -43,7 +43,7 @@ module axi_riscv_atomics
     // Add a cut between axi_riscv_amos and axi_riscv_lrsc
     parameter int unsigned N_AXI_CUT = 0,
     /// Enable full bandwidth in LRSC ID queues
-    parameter bit FULL_BANDWIDTH = 1'b0,
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (

diff --git a/src/axi_riscv_atomics_structs.sv b/src/axi_riscv_atomics_structs.sv
@@ -31,7 +31,7 @@ module axi_riscv_atomics_structs #(
   parameter int unsigned  RiscvWordWidth  = 0,
   parameter int unsigned  NAxiCuts        = 0,
   parameter int unsigned  AxiAddrLSB      = $clog2(AxiDataWidth/8),
-  parameter bit           FullBandwidth   = 0,
+  parameter bit           FullBandwidth   = 1,
   parameter type          axi_req_t       = logic,
   parameter type          axi_rsp_t       = logic
 ) (

diff --git a/src/axi_riscv_atomics_wrap.sv b/src/axi_riscv_atomics_wrap.sv
@@ -40,7 +40,7 @@ module axi_riscv_atomics_wrap #(
     // Add a cut between axi_riscv_amos and axi_riscv_lrsc
     parameter int unsigned N_AXI_CUT = 0,
     /// Enable full bandwidth in LRSC ID queues
-    parameter bit FULL_BANDWIDTH = 1'b0,
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (

diff --git a/src/axi_riscv_lrsc.sv b/src/axi_riscv_lrsc.sv
@@ -45,7 +45,7 @@ module axi_riscv_lrsc #(
     /// Enable debug prints (not synthesizable).
     parameter bit DEBUG = 1'b0,
     /// Enable full bandwidth in ID queues
-    parameter bit FULL_BANDWIDTH = 1'b0,
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (

diff --git a/src/axi_riscv_lrsc_wrap.sv b/src/axi_riscv_lrsc_wrap.sv
@@ -31,7 +31,7 @@ module axi_riscv_lrsc_wrap #(
     parameter int unsigned AXI_USER_ID_LSB = 0,    // LSB of the ID in the user signal
     parameter int unsigned AXI_ADDR_LSB = $clog2(AXI_DATA_WIDTH/8), // log2 of granularity for reservations (ignored LSBs)
     /// Enable full bandwidth in LRSC ID queues
-    parameter bit FULL_BANDWIDTH = 1'b0,
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Enable debug prints (not synthesizable).
     parameter bit DEBUG = 1'b0,
     /// Derived Parameters (do NOT change manually!)