Merge pull request #33 from pulp-platform/astral

Enable ID queues full bandwidth feature through parameter.
pulp-platform · May 8, 2024 · 27ac70f · 27ac70f
2 parents 3617819 + 3bc61a3
commit 27ac70f
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Showing 5 changed files with 19 additions and 6 deletions.
diff --git a/src/axi_riscv_atomics.sv b/src/axi_riscv_atomics.sv
@@ -42,6 +42,8 @@ module axi_riscv_atomics
     parameter int unsigned RISCV_WORD_WIDTH = 0,
     // Add a cut between axi_riscv_amos and axi_riscv_lrsc
     parameter int unsigned N_AXI_CUT = 0,
+    /// Enable full bandwidth in LRSC ID queues
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (
@@ -488,7 +490,8 @@ module axi_riscv_atomics
         .AXI_USER_AS_ID     (AXI_USER_AS_ID),
         .AXI_USER_ID_MSB    (AXI_USER_ID_MSB),
         .AXI_USER_ID_LSB    (AXI_USER_ID_LSB),
-        .AXI_ADDR_LSB       (AXI_ADDR_LSB)
+        .AXI_ADDR_LSB       (AXI_ADDR_LSB),
+        .FULL_BANDWIDTH     (FULL_BANDWIDTH)
     ) i_lrsc (
         .clk_i              ( clk_i                 ),
         .rst_ni             ( rst_ni                ),

diff --git a/src/axi_riscv_atomics_structs.sv b/src/axi_riscv_atomics_structs.sv
@@ -31,6 +31,7 @@ module axi_riscv_atomics_structs #(
   parameter int unsigned  RiscvWordWidth  = 0,
   parameter int unsigned  NAxiCuts        = 0,
   parameter int unsigned  AxiAddrLSB      = $clog2(AxiDataWidth/8),
+  parameter bit           FullBandwidth   = 1,
   parameter type          axi_req_t       = logic,
   parameter type          axi_rsp_t       = logic
 ) (
@@ -74,7 +75,8 @@ module axi_riscv_atomics_structs #(
     .AXI_USER_ID_LSB    ( AxiUserIdLsb    ),
     .AXI_ADDR_LSB       ( AxiAddrLSB      ),
     .RISCV_WORD_WIDTH   ( RiscvWordWidth  ),
-    .N_AXI_CUT          ( NAxiCuts        )
+    .N_AXI_CUT          ( NAxiCuts        ),
+    .FULL_BANDWIDTH     ( FullBandwidth   )
   ) i_axi_riscv_atomics_wrap (
     .clk_i,
     .rst_ni,

diff --git a/src/axi_riscv_atomics_wrap.sv b/src/axi_riscv_atomics_wrap.sv
@@ -39,6 +39,8 @@ module axi_riscv_atomics_wrap #(
     parameter int unsigned RISCV_WORD_WIDTH = 0,
     // Add a cut between axi_riscv_amos and axi_riscv_lrsc
     parameter int unsigned N_AXI_CUT = 0,
+    /// Enable full bandwidth in LRSC ID queues
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (
@@ -60,7 +62,8 @@ module axi_riscv_atomics_wrap #(
         .AXI_USER_ID_LSB    (AXI_USER_ID_LSB),
         .AXI_ADDR_LSB       (AXI_ADDR_LSB),
         .RISCV_WORD_WIDTH   (RISCV_WORD_WIDTH),
-        .N_AXI_CUT          (N_AXI_CUT)
+        .N_AXI_CUT          (N_AXI_CUT),
+        .FULL_BANDWIDTH     (FULL_BANDWIDTH)
     ) i_atomics (
         .clk_i           ( clk_i         ),
         .rst_ni          ( rst_ni        ),

diff --git a/src/axi_riscv_lrsc.sv b/src/axi_riscv_lrsc.sv
@@ -44,6 +44,8 @@ module axi_riscv_lrsc #(
     parameter int unsigned AXI_ADDR_LSB = $clog2(AXI_DATA_WIDTH/8), // log2 of granularity for reservations (ignored LSBs)
     /// Enable debug prints (not synthesizable).
     parameter bit DEBUG = 1'b0,
+    /// Enable full bandwidth in ID queues
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Derived Parameters (do NOT change manually!)
     localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8
 ) (
@@ -331,7 +333,7 @@ module axi_riscv_lrsc #(
         .ID_WIDTH   (AXI_ID_WIDTH),
         .CAPACITY   (AXI_MAX_READ_TXNS),
         .data_t     (r_flight_t),
-        .FULL_BW    (1'b1)
+        .FULL_BW    (FULL_BANDWIDTH)
     ) i_read_in_flight_queue (
         .clk_i              (clk_i),
         .rst_ni             (rst_ni),
@@ -515,7 +517,7 @@ module axi_riscv_lrsc #(
         .ID_WIDTH   (AXI_ID_WIDTH),
         .CAPACITY   (AXI_MAX_WRITE_TXNS),
         .data_t     (b_cmd_flat_t),
-        .FULL_BW    (1'b1)
+        .FULL_BW    (FULL_BANDWIDTH)
     ) i_b_status_queue (
         .clk_i              (clk_i),
         .rst_ni             (rst_ni),
@@ -542,7 +544,7 @@ module axi_riscv_lrsc #(
         .ID_WIDTH   (AXI_ID_WIDTH),
         .CAPACITY   (AXI_MAX_WRITE_TXNS),
         .data_t     (w_flight_t),
-        .FULL_BW    (1'b1)
+        .FULL_BW    (FULL_BANDWIDTH)
     ) i_write_in_flight_queue (
         .clk_i              (clk_i),
         .rst_ni             (rst_ni),

diff --git a/src/axi_riscv_lrsc_wrap.sv b/src/axi_riscv_lrsc_wrap.sv
@@ -30,6 +30,8 @@ module axi_riscv_lrsc_wrap #(
     parameter int unsigned AXI_USER_ID_MSB = 0,    // MSB of the ID in the user signal
     parameter int unsigned AXI_USER_ID_LSB = 0,    // LSB of the ID in the user signal
     parameter int unsigned AXI_ADDR_LSB = $clog2(AXI_DATA_WIDTH/8), // log2 of granularity for reservations (ignored LSBs)
+    /// Enable full bandwidth in LRSC ID queues
+    parameter bit FULL_BANDWIDTH = 1'b1,
     /// Enable debug prints (not synthesizable).
     parameter bit DEBUG = 1'b0,
     /// Derived Parameters (do NOT change manually!)
@@ -54,6 +56,7 @@ module axi_riscv_lrsc_wrap #(
         .AXI_USER_ID_MSB        (AXI_USER_ID_MSB),
         .AXI_USER_ID_LSB        (AXI_USER_ID_LSB),
         .AXI_ADDR_LSB           (AXI_ADDR_LSB),
+        .FULL_BANDWIDTH         (FULL_BANDWIDTH),
         .DEBUG                  (DEBUG)
     ) i_lrsc (
         .clk_i           ( clk_i         ),