AD9910 dds synthesizer firmware documentation
=============================================


Overview
--------

This is the documentation for the synthesizer board which is
meant to work with programmable pulse generator as designed by
Paul Pham

link:[http://pulse-sequencer.sf.net]

The features of the board are:

- Onboard Cyclone II FPGA for increased flexibility
- AD9910 DDS with 14Bit DAC and 1Gs/s clock
- AD9744 DAC and AD8367 VGA for pulse shaping
- 32Bit LVDS bus for high speed data transfer


This documentation is focused on the programming of the FPGA.
This is accomplished in the VHDL hardware description language.

This board is only supported by the sequencer2 python compiler/server.

The source code is spread over following files:
`------------------------`---------------------------
Filename                  Function
-----------------------------------------------------
dds_controller.vhd        top entity, opcode decoding
ddslib.vhd                configuration, opcode definition
dds_serial.vhd            parallel to serial decoding
fifo.vhd                  FIFO megafunction intance
phase_register.vhd        phase registers
-----------------------------------------------------

The VHDL files can be compiled with the free quartus II web edition which is
available at
link:[http://www.altera.com/]

Compilation
~~~~~~~~~~~
To compile the firmware open the dds_controller.qpf file in quartus II and press ctrl - L

To program the firmware on the FPGA open the Programmer in quartus II and select
active-serial-programming. Add the file dds_controller.pof for programming and press start.


Bus definition
~~~~~~~~~~~~~~
The control bits in the instruction word are:

`---------------------------------------`--------------------------
Function                                  Bus bits used
-------------------------------------------------------------------
opcode                                    (31:27)
data available                            (26)
address (not implemented)                 (25:22)
phase register wren / DRCTL               (21)
phase register set current /DHOLD         (20)
phase register address                    (16:19)
dds_drctl                                 (16)
dds_drhold                                (17)
dds_ramp_config                           (18)
data bus                                  (15:0)
--------------------------------------------------------------------

Write process timing:
~~~~~~~~~~~~~~~~~~~~~

A write process on the LVDS bus is specified with 3 clock cycles of the PCP-FPGA.
The length of one cycle is 10ns.

- Set the data bus , bits(15:0)
- Set opcode, dds address and other bits except data available bit(25)
- Set data available bit(25)

The data available bit should be unset after one clock cycle.

This is a conservative and hopefully save method to write data to the bus.

DDS interface
~~~~~~~~~~~~~

The ad9910 dds has internal registers which determine the mode of operation.
These registers have to be programmed over a serial SPI interface.
To speed up the data transfer from the PCP to the DDS the data is transmitted over
the parallel board to the FPGA on the DDS board. This data is then written into the
DDS via the serial interface.
Each configuration register has to be programmed at once. As the registers are up to
64Bits wide the data from the PCP is stored in a FIFO implemented the FPGA on the
DDS board.

A write cycle to  the DDS is accomplished as follows:

- The data is split in 16bit words
- This words are transmitted from the PCP to the FPGA
- The 8 bit address word of the register is transmitted
- The FIFO is read until it is empty


Testing the board:
------------------

Connecting the board
~~~~~~~~~~~~~~~~~~~~

- Connect 5V to the analog and digital power supply
- Connect 10V..12V to the analog 10V suply.
- Connect 100MHz to the T_DDS_FPGA connector
- Connect 800MHz to the connector P1
- Set the jumpers as shown in the image

INSERT IMAGE OF BOARD HERE

To test the functionality of the DDS board following procedure is recommended.

Test the Voltage regulators
~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Connect a single board to a power supply with an adjustable current limit.
- Set the current limit to about 10mA and the Voltage to 6V
- Turn up the curent limit. If the board draws more than 400mA there is most
likely a short circuit on the board.
- Check the desired output voltage with an oscilloscope/multimeter

 INSERT VOLTAGES AND IC NUMBERS HERE

Test the LVDS Bus
~~~~~~~~~~~~~~~~~

To test the functionality of the LVDS Bus a working sequencer-rev.C board and
a suitable breakout board is needed.

Furthermore a JTAG download cable and a quartusII installation is necessary

- Activate the test_lvds_bus.stp SignalTap file in quartusII
- Compile the VHDL source with quartusII
- Connect the JTAG cable to the JTAG board (J2)
- Program the FPGA (with JTAG, NOT active serial programming)
- Start ipython in the sequencer directory and execute following code:

-------------------------------------
from tests.test_hardware import *
t1 = HardwareTests(nonet=True)
t1.test_lvds_bus()
-------------------------------------

- Ensure that the bus values are correct.

INSERT SCREENSHOT

Another quick (but incomplete) test of the LVDS Bus can be performed by generating
DAC events with the sequencer and checking the output voltage of the DAC.

Test the DDS
~~~~~~~~~~~~
- Start ipython in the sequencer directory and execute following code:

-------------------------------------
from tests.test_hardware import *
t1 = HardwareTests(nonet=True)
t1.test_dds_simple()
-------------------------------------

- Test the output of the DDS.

INSERT DATA HERE

If these tests were succesfully you most probably have a working system.


Test phase coherent switching
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Use a fixed frequency source as reference
- Switch the DDS board to the same frequency with different phases.
- Check the pghase relation of the two signals with an RF-mixer


Programming guide
-------------------

Writing a register on the dds
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Split the data in 16bit words
- Write the data subsequentially into the FIFO with the fifo write insn
- Set the upper 8 bits of the data bus to the desired address
- Provide the dds address Opcode and the address data until the register is set

Load the phase register
~~~~~~~~~~~~~~~~~~~~~~~
- Split the frequency tuning word into two 16Bit words
- Write the lower word with wren=0 and set current=0 and the load phase opcode
- Write the upper word with wren=0 and set current=1 and the load phase opcode
- Set the phase register address bits
- Write load_wren_opcode and set_current=1 do not change data on pins 0:15

Phase coherent switching
~~~~~~~~~~~~~~~~~~~~~~~~
This is not properly implemented yet

- Set the dds frequency either by writing the register or the profile
- Provide the pulse phase opcode
- Wait 4 cycles
- Provide the dds update opcode

Set the DAC
~~~~~~~~~~~

- Set the data bus bits (13:0)
- Provide the dac amplitude opcode

Ramp Control
~~~~~~~~~~~~

Set the registers over the serial port. Control then the drhold and drhold pins of the DDS.

Preliminary Opcode specification
--------------------------------

Already implemented opcodes
~~~~~~~~~~~~~~~~~~~~~~~~~~~

`--------------`---------`-----------------------------------
Name            Opcode    Function
-------------------------------------------------------------
nop             0x0       Do nothing
dds_addr        0x1       Write content of FIFO to given DDS
fifo_wr         0x2       Write lower 16bits to FIFO
dds_profile     0x3       Set the DDS profile bits
dac_amplitude   0x7       Set the DAC for the VGA
load_phase      0xa       Load the phase register
pulse_phase     0xb       Write given phase register to DDS
fifo_reset      0x1f      Clear the FIFO
dds_update      0x4       Update the DDS or control ramp generator
-------------------------------------------------------------

Proposed opcodes
~~~~~~~~~~~~~~~~

`------------`-------------------------------
Name          Function
---------------------------------------------
dds_sweep     Start/Stop a DDS sweep
dds_ramp      Generate a DDS amplitude ramp
all_reset     Reset the FIFO and the DDS
---------------------------------------------

License
-------

(c) 2008 Philipp Schindler.

This work is published under the GNU Public License

The file phase_register.vhd is copyright by Paul Pham
and released under the BSD License.