riscv: add riscv arch support

src/GNUmakefile

@@ -14,15 +14,19 @@ STRIP    = $(CROSS_COMPILE)strip
 OBJCOPY  = $(CROSS_COMPILE)objcopy
 OBJDUMP  = $(CROSS_COMPILE)objdump
 PYTHON   = python3
+ARCH	 = $(shell uname -m)
 
 HAS_SWIG := $(shell swig -version 2>/dev/null)
 PYTHON_MAJOR_VERSION = $(shell ${PYTHON} -c "import sys; print(sys.version_info.major)" 2>/dev/null)
 PYTHON_EMBED = $(shell ${PYTHON} -c "import sys; print('--embed' if sys.hexversion > 0x03080000 else '')" 2>/dev/null)
 HAS_PYTHON_CONFIG := $(shell ${PYTHON}-config --ldflags ${PYTHON_EMBED} 2>/dev/null)
 
 CPPFLAGS += -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -I. -I$(VPATH) -I$(VPATH)/../lib/uthash/include
-CFLAGS   += -g -Wall -Wextra -O2
+ifeq ($(ARCH),riscv64)
+CFLAGS	 += -g -Wall -Wextra -O0
+else
 CFLAGS   += $(shell pkg-config --cflags talloc)
+endif
 LDFLAGS  += -Wl,-z,noexecstack
 LDFLAGS  += $(shell pkg-config --libs talloc)
 

src/arch.h

@@ -38,7 +38,7 @@ typedef unsigned char byte_t;
 #define OFFSETOF_STATX_UID 20
 #define OFFSETOF_STATX_GID 24
 
-#if !defined(ARCH_X86_64) && !defined(ARCH_ARM_EABI) && !defined(ARCH_X86) && !defined(ARCH_SH4)
+#if !defined(ARCH_X86_64) && !defined(ARCH_ARM_EABI) && !defined(ARCH_X86) && !defined(ARCH_SH4) && !defined(ARCH_RISCV64)
 #    if defined(__x86_64__)
 #        define ARCH_X86_64 1
 #    elif defined(__ARM_EABI__)
@@ -51,6 +51,8 @@ typedef unsigned char byte_t;
 #        define ARCH_X86 1
 #    elif defined(__SH4__)
 #        define ARCH_SH4 1
+#    elif defined(__riscv) && __riscv_flen == 64
+#        define ARCH_RISCV64 1
 #    else
 #        error "Unsupported architecture"
 #    endif
@@ -110,6 +112,25 @@ typedef unsigned char byte_t;
     #define EXEC_PIC_ADDRESS   0x0f000000
     #define INTERP_PIC_ADDRESS 0x1f000000
 
+#elif defined(ARCH_RISCV64)
+
+    #define SYSNUMS_HEADER1 "syscall/sysnums-riscv64.h"
+    #define SYSNUMS_ABI1    sysnums_riscv64
+    #define SYSTRAP_SIZE 4
+
+    #define SECCOMP_ARCHS { { .value = AUDIT_ARCH_RISCV64, .nb_abis = 1, .abis = { ABI_DEFAULT } } }
+
+    #define user_regs_struct user_regs_struct 
+    #define HOST_ELF_MACHINE {243};
+    #define RED_ZONE_SIZE 0
+    #define OFFSETOF_STAT_UID_32 0
+    #define OFFSETOF_STAT_GID_32 0
+
+    #define EXEC_PIC_ADDRESS   0x10000
+
+    #define LOADER_ADDRESS     0x10000000
+    #define INTERP_PIC_ADDRESS 0x1f000000
+
 #elif defined(ARCH_ARM64)
 
     #define SYSNUMS_HEADER1 "syscall/sysnums-arm64.h"

src/loader/assembly-riscv64.h

@@ -0,0 +1,90 @@
+/* -*- c-set-style: "K&R"; c-basic-offset: 8 -*-
+ *
+ * This file is part of PRoot.
+ *
+ * Copyright (C) 2024 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA.
+ */
+
+/*
+ * - the instruction pointer (pc)
+ * - the stack pointer (sp)
+ * - the rtld_fini pointer (a0)
+ */
+#define BRANCH(stack_pointer, destination) do {			\
+	asm volatile ("add sp, %0, zero"::"r"(stack_pointer):"memory"); \
+	asm volatile ("add a0, zero, zero");			\
+	asm volatile ("jr %0"::"r"(destination):"memory","a0");	\
+	__builtin_unreachable();				\
+	} while (0)
+
+#define PREPARE_ARGS_1(arg1_)				\
+	register word_t arg1 asm("a0") = arg1_;		\
+
+#define PREPARE_ARGS_3(arg1_, arg2_, arg3_)		\
+	PREPARE_ARGS_1(arg1_)				\
+	register word_t arg2 asm("a1") = arg2_;		\
+	register word_t arg3 asm("a2") = arg3_;		\
+
+#define PREPARE_ARGS_4(arg1_, arg2_, arg3_, arg4_)	\
+	PREPARE_ARGS_3(arg1_, arg2_, arg3_)		\
+	register word_t arg4 asm("a3") = arg4_;		\
+
+#define PREPARE_ARGS_6(arg1_, arg2_, arg3_, arg4_, arg5_, arg6_)	\
+	PREPARE_ARGS_4(arg1_, arg2_, arg3_, arg4_)			\
+	register word_t arg5 asm("a4") = arg5_;				\
+	register word_t arg6 asm("a5") = arg6_;
+
+
+#define OUTPUT_CONTRAINTS_1			\
+	"r" (arg1)
+
+#define OUTPUT_CONTRAINTS_3			\
+	OUTPUT_CONTRAINTS_1,			\
+	"r" (arg2), "r" (arg3)
+
+#define OUTPUT_CONTRAINTS_4			\
+	OUTPUT_CONTRAINTS_3,			\
+	"r" (arg4)
+
+#define OUTPUT_CONTRAINTS_6			\
+	OUTPUT_CONTRAINTS_4,			\
+	"r" (arg5), "r" (arg6)
+
+
+
+#define SYSCALL(number_, nb_args, args...)				\
+	({								\
+		register word_t number asm("a7") = number_;		\
+		register word_t result asm("a0");			\
+	 	PREPARE_ARGS_##nb_args(args)				\
+			asm volatile (					\
+				"ecall	        	\n\t"		\
+				: "=r" (result)				\
+				: "r" (number),				\
+				OUTPUT_CONTRAINTS_##nb_args		\
+				: "memory");				\
+			result;						\
+	})
+
+#define OPENAT	56
+#define CLOSE	57
+#define MMAP	222
+#define EXECVE	221
+#define EXIT	93
+#define PRCTL   167
+#define MPROTECT 226

src/loader/loader.c

@@ -43,6 +43,8 @@
 #    include "loader/assembly-x86.h"
 #elif defined(ARCH_ARM64)
 #    include "loader/assembly-arm64.h"
+#elif defined(ARCH_RISCV64)
+#	 include "loader/assembly-riscv64.h"
 #else
 #    error "Unsupported architecture"
 #endif

src/ptrace/ptrace.c

@@ -58,6 +58,10 @@
 #define user_fpregs_struct user_fpsimd_struct
 #endif
 
+#if defined(ARCH_RISCV64)
+#define user_fpregs_struct __riscv_d_ext_state
+#endif
+
 static const char *stringify_ptrace(PTRACE_REQUEST_TYPE request)
 {
 #define CASE_STR(a) case a: return #a; break;

src/ptrace/user.c

@@ -30,6 +30,12 @@
 #include "ptrace/user.h"
 #include "cli/note.h"
 
+#if defined(ARCH_RISCV64) && defined(__GLIBC__)
+/* ptrace user_regs in glibc for riscv is in asm/ptrace.h */
+/* not in sys/user.h */
+#include <asm/ptrace.h>
+#endif
+
 #if defined(ARCH_X86_64)
 
 /**