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[hw] Make verilator build work for both earlgrey and englishbreakfast
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The two tops do not quite use the same flow, in particular they use
different flags to specify the fileset. This requires to tweak the
fusesoc rule to make it more general.

Signed-off-by: Amaury Pouly <[email protected]>
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pamaury committed Sep 30, 2024
1 parent f1ee33f commit d04de16
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Showing 2 changed files with 25 additions and 12 deletions.
28 changes: 22 additions & 6 deletions hw/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -42,10 +42,24 @@ fusesoc_build(
],
data = ["//hw/ip/otbn:all_files"],
make_options = ":make_options",
output_groups = {
"binary": ["sim-verilator/Vchip_sim_tb"],
},
systems = ["lowrisc:dv:chip_verilator_sim"],
output_groups = select({
"//sw/device:is_english_breakfast": {
"binary": ["sim-verilator/Vchip_englishbreakfast_verilator"],
},
"//conditions:default": {
"binary": ["sim-verilator/Vchip_sim_tb"],
},
}),
systems = select({
"//sw/device:is_english_breakfast": ["lowrisc:systems:chip_englishbreakfast_verilator"],
"//conditions:default": ["lowrisc:dv:chip_verilator_sim"],
}),
# Note: the `fileset_top(gen)` flags used below are specific to the OpenTitan
# project to select the correct RTL fileset.
use_flags = select({
"//sw/device:is_english_breakfast": ["fileset_topgen"],
"//conditions:default": ["fileset_top"],
}),
tags = [
"manual",
"verilator",
Expand Down Expand Up @@ -114,9 +128,11 @@ filegroup(
"//:tool_requirements.py",
"//hw/ip:all_files",
"//hw/ip_templates:all_files",
"//hw/top_earlgrey:all_files",
"//util:check_tool_requirements.py",
],
] + select({
"//sw/device:is_english_breakfast": ["//hw/top_englishbreakfast:all_files"],
"//conditions:default": ["//hw/top_earlgrey:all_files"],
}),
visibility = ["//visibility:public"],
)

Expand Down
9 changes: 3 additions & 6 deletions rules/fusesoc.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -66,10 +66,8 @@ def _fusesoc_build_impl(ctx):
format_each = "--cores-root=%s",
)

args.add_all([
"run",
"--flag=fileset_top",
])
args.add("run")
args.add_all(["--flag={}".format(f) for f in ctx.attr.use_flags])
args.add(ctx.attr.target, format = "--target=%s")
args.add_all([
"--setup",
Expand All @@ -80,8 +78,6 @@ def _fusesoc_build_impl(ctx):
args.add_all(ctx.attr.systems)
args.add_all(flags)

# Note: the `fileset_top` flag used above is specific to the OpenTitan
# project to select the correct RTL fileset.
ctx.actions.run(
mnemonic = "FuseSoC",
outputs = outputs,
Expand Down Expand Up @@ -109,6 +105,7 @@ fusesoc_build = rule(
"data": attr.label_list(allow_files = True, doc = "Files needed at runtime"),
"target": attr.string(mandatory = True, doc = "Target name (e.g. 'sim')"),
"systems": attr.string_list(mandatory = True, doc = "Systems to build"),
"use_flags": attr.string_list(doc = "Custom fusesoc use flags"),
"flags": attr.string_list(doc = "Flags controlling the FuseSOC system build"),
"output_groups": attr.string_list_dict(
allow_empty = True,
Expand Down

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